X86 Opcode and Instruction Reference Home

Other editions: coder64, coder, geek32, geek64, geek

one-byte opcodes index:

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF

two-byte opcodes (0F..) index:

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
pf 0F po so o proc st m rl x mnemonic op1 op2 op3 op4 iext tested f modif f def f undef f f values description, notes                                                  
00 r L ADD r/m8 r8 o..szapc o..szapc Add
01 r L ADD r/m16/32 r16/32 o..szapc o..szapc Add
02 r ADD r8 r/m8 o..szapc o..szapc Add
03 r ADD r16/32 r/m16/32 o..szapc o..szapc Add
04 ADD AL imm8 o..szapc o..szapc Add
05 ADD eAX imm16/32 o..szapc o..szapc Add
06 PUSH ES Push Word, Doubleword or Quadword Onto the Stack
07 POP ES Pop a Value from the Stack
08 r L OR r/m8 r8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
09 r L OR r/m16/32 r16/32 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0A r OR r8 r/m8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0B r OR r16/32 r/m16/32 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0C OR AL imm8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0D OR eAX imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
0E PUSH CS Push Word, Doubleword or Quadword Onto the Stack
0F 02+ Two-byte Instructions
10 r L ADC r/m8 r8 .......c o..szapc o..szapc Add with Carry
11 r L ADC r/m16/32 r16/32 .......c o..szapc o..szapc Add with Carry
12 r ADC r8 r/m8 .......c o..szapc o..szapc Add with Carry
13 r ADC r16/32 r/m16/32 .......c o..szapc o..szapc Add with Carry
14 ADC AL imm8 .......c o..szapc o..szapc Add with Carry
15 ADC eAX imm16/32 .......c o..szapc o..szapc Add with Carry
16 PUSH SS Push Word, Doubleword or Quadword Onto the Stack
17 POP SS Pop a Value from the Stack
18 r L SBB r/m8 r8 .......c o..szapc o..szapc Integer Subtraction with Borrow
19 r L SBB r/m16/32 r16/32 .......c o..szapc o..szapc Integer Subtraction with Borrow
1A r SBB r8 r/m8 .......c o..szapc o..szapc Integer Subtraction with Borrow
1B r SBB r16/32 r/m16/32 .......c o..szapc o..szapc Integer Subtraction with Borrow
1C SBB AL imm8 .......c o..szapc o..szapc Integer Subtraction with Borrow
1D SBB eAX imm16/32 .......c o..szapc o..szapc Integer Subtraction with Borrow
1E PUSH DS Push Word, Doubleword or Quadword Onto the Stack
1F POP DS Pop a Value from the Stack
20 r L AND r/m8 r8 o..szapc o..sz.pc .....a.. o......c Logical AND
21 r L AND r/m16/32 r16/32 o..szapc o..sz.pc .....a.. o......c Logical AND
22 r AND r8 r/m8 o..szapc o..sz.pc .....a.. o......c Logical AND
23 r AND r16/32 r/m16/32 o..szapc o..sz.pc .....a.. o......c Logical AND
24 AND AL imm8 o..szapc o..sz.pc .....a.. o......c Logical AND
25 AND eAX imm16/32 o..szapc o..sz.pc .....a.. o......c Logical AND
26 ES ES ES segment override prefix
26 P4+ undefined (use with any branch instruction is reserved)
27 DAA AL .....a.c o..szapc ...szapc o....... Decimal Adjust AL after Addition
28 r L SUB r/m8 r8 o..szapc o..szapc Subtract
29 r L SUB r/m16/32 r16/32 o..szapc o..szapc Subtract
2A r SUB r8 r/m8 o..szapc o..szapc Subtract
2B r SUB r16/32 r/m16/32 o..szapc o..szapc Subtract
2C SUB AL imm8 o..szapc o..szapc Subtract
2D SUB eAX imm16/32 o..szapc o..szapc Subtract
2E CS CS CS segment override prefix
2F DAS AL .....a.c o..szapc ...szapc o....... Decimal Adjust AL after Subtraction
30 r L XOR r/m8 r8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
31 r L XOR r/m16/32 r16/32 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
32 r XOR r8 r/m8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
33 r XOR r16/32 r/m16/32 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
34 XOR AL imm8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
35 XOR eAX imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
36 SS SS SS segment override prefix
36 P4+ undefined (use with any branch instruction is reserved)
37 AAA AL AH .....a.. o..szapc .....a.c o..sz.p. ASCII Adjust After Addition
38 r CMP r/m8 r8 o..szapc o..szapc Compare Two Operands
39 r CMP r/m16/32 r16/32 o..szapc o..szapc Compare Two Operands
3A r CMP r8 r/m8 o..szapc o..szapc Compare Two Operands
3B r CMP r16/32 r/m16/32 o..szapc o..szapc Compare Two Operands
3C CMP AL imm8 o..szapc o..szapc Compare Two Operands
3D CMP eAX imm16/32 o..szapc o..szapc Compare Two Operands
3E DS DS DS segment override prefix
3F AAS AL AH .....a.. o..szapc .....a.c o..sz.p. ASCII Adjust AL After Subtraction
40+r INC r16/32 o..szap. o..szap. Increment by 1
48+r DEC r16/32 o..szap. o..szap. Decrement by 1
50+r PUSH r16/32 Push Word, Doubleword or Quadword Onto the Stack
58+r POP r16/32 Pop a Value from the Stack
60 01+ PUSHA AX CX DX ... Push All General-Purpose Registers
60 03+ PUSHAD EAX ECX EDX ... Push All General-Purpose Registers
61 01+ POPA DI SI BP ... Pop All General-Purpose Registers
61 03+ POPAD EDI ESI EBP ... Pop All General-Purpose Registers
62 r 01+ f BOUND r16/32 m16/32&16/32 eFlags ..i..... ..i..... ..i..... Check Array Index Against Bounds
63 r 02+ ARPL r/m16 r16 ....z... ....z... Adjust RPL Field of Segment Selector
64 03+ FS FS FS segment override prefix
64 P4+ undefined (used only with Jcc instructions)
65 03+ GS GS GS segment override prefix
65 P4+ undefined (used only with Jcc instructions)
66 no mnemonic Operand-size override prefix
66 P4+ M no mnemonic sse2 Precision-size override prefix
67 no mnemonic Address-size override prefix
68 01+ PUSH imm16/32 Push Word, Doubleword or Quadword Onto the Stack
69 r 01+ IMUL r16/32 r/m16/32 imm16/32 o..szapc o......c ...szap. Signed Multiply
6A 01+ PUSH imm8 Push Word, Doubleword or Quadword Onto the Stack
6B r 01+ IMUL r16/32 r/m16/32 imm8 o..szapc o......c ...szap. Signed Multiply
6C 01+ f1 INS m8 DX .d...... Input from Port to String
INSB m8 DX
6D 01+ f1 INS m16 DX .d...... Input from Port to String
INSW m16 DX
6D 03+ f1 INS m16/32 DX .d...... Input from Port to String
INSD m32 DX
6E 01+ f1 OUTS DX m8 .d...... Output String to Port
OUTSB DX m8
6F 01+ f1 OUTS DX m16 .d...... Output String to Port
OUTSW DX m16
6F 03+ f1 OUTS DX m16/32 .d...... Output String to Port
OUTSD DX m32
70 JO rel8 o....... Jump short if overflow (OF=1)
71 JNO rel8 o....... Jump short if not overflow (OF=0)
72 JB rel8 .......c Jump short if below/not above or equal/carry (CF=1)
JNAE rel8
JC rel8
73 JNB rel8 .......c Jump short if not below/above or equal/not carry (CF=0)
JAE rel8
JNC rel8
74 JZ rel8 ....z... Jump short if zero/equal (ZF=0)
JE rel8
75 JNZ rel8 ....z... Jump short if not zero/not equal (ZF=1)
JNE rel8
76 JBE rel8 ....z..c Jump short if below or equal/not above (CF=1 AND ZF=1)
JNA rel8
77 JNBE rel8 ....z..c Jump short if not below or equal/above (CF=0 AND ZF=0)
JA rel8
78 JS rel8 ...s.... Jump short if sign (SF=1)
79 JNS rel8 ...s.... Jump short if not sign (SF=0)
7A JP rel8 ......p. Jump short if parity/parity even (PF=1)
JPE rel8
7B JNP rel8 ......p. Jump short if not parity/parity odd
JPO rel8
7C JL rel8 o..s.... Jump short if less/not greater (SF!=OF)
JNGE rel8
7D JNL rel8 o..s.... Jump short if not less/greater or equal (SF=OF)
JGE rel8
7E JLE rel8 o..sz... Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel8
7F JNLE rel8 o..sz... Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel8
80 0 L ADD r/m8 imm8 o..szapc o..szapc Add
80 1 L OR r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
80 2 L ADC r/m8 imm8 .......c o..szapc o..szapc Add with Carry
80 3 L SBB r/m8 imm8 .......c o..szapc o..szapc Integer Subtraction with Borrow
80 4 L AND r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical AND
80 5 L SUB r/m8 imm8 o..szapc o..szapc Subtract
80 6 L XOR r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
80 7 CMP r/m8 imm8 o..szapc o..szapc Compare Two Operands
81 0 L ADD r/m16/32 imm16/32 o..szapc o..szapc Add
81 1 L OR r/m16/32 imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
81 2 L ADC r/m16/32 imm16/32 .......c o..szapc o..szapc Add with Carry
81 3 L SBB r/m16/32 imm16/32 .......c o..szapc o..szapc Integer Subtraction with Borrow
81 4 L AND r/m16/32 imm16/32 o..szapc o..sz.pc .....a.. o......c Logical AND
81 5 L SUB r/m16/32 imm16/32 o..szapc o..szapc Subtract
81 6 L XOR r/m16/32 imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
81 7 CMP r/m16/32 imm16/32 o..szapc o..szapc Compare Two Operands
82 0 L ADD r/m8 imm8 o..szapc o..szapc Add
82 1 L OR r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
82 2 L ADC r/m8 imm8 .......c o..szapc o..szapc Add with Carry
82 3 L SBB r/m8 imm8 .......c o..szapc o..szapc Integer Subtraction with Borrow
82 4 L AND r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical AND
82 5 L SUB r/m8 imm8 o..szapc o..szapc Subtract
82 6 L XOR r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
82 7 CMP r/m8 imm8 o..szapc o..szapc Compare Two Operands
83 0 L ADD r/m16/32 imm8 o..szapc o..szapc Add
83 1 03+ L OR r/m16/32 imm8 o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
83 2 L ADC r/m16/32 imm8 .......c o..szapc o..szapc Add with Carry
83 3 L SBB r/m16/32 imm8 .......c o..szapc o..szapc Integer Subtraction with Borrow
83 4 03+ L AND r/m16/32 imm8 o..szapc o..sz.pc .....a.. o......c Logical AND
83 5 L SUB r/m16/32 imm8 o..szapc o..szapc Subtract
83 6 03+ L XOR r/m16/32 imm8 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
83 7 CMP r/m16/32 imm8 o..szapc o..szapc Compare Two Operands
84 r TEST r/m8 r8 o..szapc o..sz.pc .....a.. o......c Logical Compare
85 r TEST r/m16/32 r16/32 o..szapc o..sz.pc .....a.. o......c Logical Compare
86 r L XCHG r8 r/m8 Exchange Register/Memory with Register
87 r L XCHG r16/32 r/m16/32 Exchange Register/Memory with Register
88 r MOV r/m8 r8 Move
89 r MOV r/m16/32 r16/32 Move
8A r MOV r8 r/m8 Move
8B r MOV r16/32 r/m16/32 Move
8C r MOV m16 Sreg Move
MOV r16/32 Sreg
8D r LEA r16/32 m Load Effective Address
8E r MOV Sreg r/m16 Move
8F 0 POP r/m16/32 Pop a Value from the Stack
90+r XCHG r16/32 eAX Exchange Register/Memory with Register
90 NOP No Operation
F3 90 P4+ PAUSE sse2 Spin Loop Hint
98 CBW AX AL Convert Byte to Word
98 03+ CWDE EAX AX Convert Word to Doubleword
99 CWD DX AX Convert Word to Doubleword
99 03+ CDQ EDX EAX Convert Doubleword to Quadword
9A CALLF ptr16:16/32 Call Procedure
9B FWAIT 0123 0123 Check pending unmasked floating-point exceptions
WAIT
9B no mnemonic 0123 0123 Wait Prefix
9C PUSHF Flags odiszapc Push FLAGS Register onto the Stack
9C 03+ PUSHFD EFlags odiszapc Push eFLAGS Register onto the Stack
9D POPF Flags odiszapc odiszapc Pop Stack into FLAGS Register
9D 03+ POPFD EFlags odiszapc odiszapc Pop Stack into eFLAGS Register
9E SAHF AH ...szapc ...szapc Store AH into Flags
9F LAHF AH ...szapc Load Status Flags into AH Register
A0 MOV AL moffs8 Move
A1 MOV eAX moffs16/32 Move
A2 MOV moffs8 AL Move
A3 MOV moffs16/32 eAX Move
A4 MOVS m8 m8 .d...... Move Data from String to String
MOVSB m8 m8
A5 MOVS m16 m16 .d...... Move Data from String to String
MOVSW m16 m16
A5 03+ MOVS m16/32 m16/32 .d...... Move Data from String to String
MOVSD m32 m32
A6 CMPS m8 m8 .d...... o..szapc o..szapc Compare String Operands
CMPSB m8 m8
A7 CMPS m16 m16 .d...... o..szapc o..szapc Compare String Operands
CMPSW m16 m16
A7 03+ CMPS m16/32 m16/32 .d...... o..szapc o..szapc Compare String Operands
CMPSD m32 m32
A8 TEST AL imm8 o..szapc o..sz.pc .....a.. o......c Logical Compare
A9 TEST eAX imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Compare
AA STOS m8 AL .d...... Store String
STOSB m8 AL
AB STOS m16 AX .d...... Store String
STOSW m16 AX
AB 03+ STOS m16/32 eAX .d...... Store String
STOSD m32 EAX
AC LODS AL m8 .d...... Load String
LODSB AL m8
AD LODS AX m16 .d...... Load String
LODSW AX m16
AD 03+ LODS eAX m16/32 .d...... Load String
LODSD EAX m32
AE SCAS m8 AL .d...... o..szapc o..szapc Scan String
SCASB m8 AL
AF SCAS m16 AX .d...... o..szapc o..szapc Scan String
SCASW m16 AX
AF 03+ SCAS m16/32 eAX .d...... o..szapc o..szapc Scan String
SCASD m32 EAX
B0+r MOV r8 imm8 Move
B8+r MOV r16/32 imm16/32 Move
C0 0 01+ ROL r/m8 imm8 o..szapc o..szapc o....... Rotate
C0 1 01+ ROR r/m8 imm8 o..szapc o..szapc o....... Rotate
C0 2 01+ RCL r/m8 imm8 .......c o..szapc o..szapc o....... Rotate
C0 3 01+ RCR r/m8 imm8 .......c o..szapc o..szapc o....... Rotate
C0 4 01+ SHL r/m8 imm8 o..szapc o..sz.pc o....a.c Shift
SAL r/m8 imm8
C0 5 01+ SHR r/m8 imm8 o..szapc o..sz.pc o....a.c Shift
C0 6 01+ U1 SAL r/m8 imm8 o..szapc o..sz.pc o....a.c Shift
SHL r/m8 imm8
C0 7 01+ SAR r/m8 imm8 o..szapc o..sz.pc o....a.. Shift
C1 0 01+ ROL r/m16/32 imm8 o..szapc o..szapc o....... Rotate
C1 1 01+ ROR r/m16/32 imm8 o..szapc o..szapc o....... Rotate
C1 2 01+ RCL r/m16/32 imm8 .......c o..szapc o..szapc o....... Rotate
C1 3 01+ RCR r/m16/32 imm8 .......c o..szapc o..szapc o....... Rotate
C1 4 01+ SHL r/m16/32 imm8 o..szapc o..sz.pc o....a.c Shift
SAL r/m16/32 imm8
C1 5 01+ SHR r/m16/32 imm8 o..szapc o..sz.pc o....a.c Shift
C1 6 01+ U1 SAL r/m16/32 imm8 o..szapc o..sz.pc o....a.c Shift
SHL r/m16/32 imm8
C1 7 01+ SAR r/m16/32 imm8 o..szapc o..sz.pc o....a.. Shift
C2 RETN imm16 Return from procedure
C3 RETN Return from procedure
C4 r LES ES r16/32 m16:16/32 Load Far Pointer
C5 r LDS DS r16/32 m16:16/32 Load Far Pointer
C6 0 MOV r/m8 imm8 Move
C7 0 MOV r/m16/32 imm16/32 Move
C8 01+ ENTER eBP imm16 imm8 Make Stack Frame for Procedure Parameters
C9 01+ LEAVE eBP High Level Procedure Exit
CA f RETF imm16 Return from procedure
CB f RETF Return from procedure
CC f INT 3 eFlags ..i..... ..i..... ..i..... Call to Interrupt Procedure
CD f INT imm8 eFlags ..i..... ..i..... ..i..... Call to Interrupt Procedure
CE f INTO eFlags o....... ..i..... ..i..... ..i..... Call to Interrupt Procedure
CF f IRET Flags odiszapc odiszapc Interrupt Return
CF 03+ f IRETD EFlags odiszapc odiszapc Interrupt Return
D0 0 ROL r/m8 1 o..szapc o..szapc Rotate
D0 1 ROR r/m8 1 o..szapc o..szapc Rotate
D0 2 RCL r/m8 1 .......c o..szapc o..szapc Rotate
D0 3 RCR r/m8 1 .......c o..szapc o..szapc Rotate
D0 4 SHL r/m8 1 o..szapc o..sz.pc .....a.. Shift
SAL r/m8 1
D0 5 SHR r/m8 1 o..szapc o..sz.pc .....a.. Shift
D0 6 U1 SAL r/m8 1 o..szapc o..sz.pc .....a.. Shift
SHL r/m8 1
D0 7 SAR r/m8 1 o..szapc o..sz.pc .....a.. Shift
D1 0 ROL r/m16/32 1 o..szapc o..szapc Rotate
D1 1 ROR r/m16/32 1 o..szapc o..szapc Rotate
D1 2 RCL r/m16/32 1 .......c o..szapc o..szapc Rotate
D1 3 RCR r/m16/32 1 .......c o..szapc o..szapc Rotate
D1 4 SHL r/m16/32 1 o..szapc o..sz.pc .....a.. Shift
SAL r/m16/32 1
D1 5 SHR r/m16/32 1 o..szapc o..sz.pc .....a.. Shift
D1 6 U1 SAL r/m16/32 1 o..szapc o..sz.pc .....a.. Shift
SHL r/m16/32 1
D1 7 SAR r/m16/32 1 o..szapc o..sz.pc .....a.. Shift
D2 0 ROL r/m8 CL o..szapc o..szapc o....... Rotate
D2 1 ROR r/m8 CL o..szapc o..szapc o....... Rotate
D2 2 RCL r/m8 CL .......c o..szapc o..szapc o....... Rotate
D2 3 RCR r/m8 CL .......c o..szapc o..szapc o....... Rotate
D2 4 SHL r/m8 CL o..szapc o..sz.pc o....a.c Shift
SAL r/m8 CL
D2 5 SHR r/m8 CL o..szapc o..sz.pc o....a.c Shift
D2 6 U1 SAL r/m8 CL o..szapc o..sz.pc o....a.c Shift
SHL r/m8 CL
D2 7 SAR r/m8 CL o..szapc o..sz.pc o....a.. Shift
D3 0 ROL r/m16/32 CL o..szapc o..szapc o....... Rotate
D3 1 ROR r/m16/32 CL o..szapc o..szapc o....... Rotate
D3 2 RCL r/m16/32 CL .......c o..szapc o..szapc o....... Rotate
D3 3 RCR r/m16/32 CL .......c o..szapc o..szapc o....... Rotate
D3 4 SHL r/m16/32 CL o..szapc o..sz.pc o....a.c Shift
SAL r/m16/32 CL
D3 5 SHR r/m16/32 CL o..szapc o..sz.pc o....a.c Shift
D3 6 U1 SAL r/m16/32 CL o..szapc o..sz.pc o....a.c Shift
SHL r/m16/32 CL
D3 7 SAR r/m16/32 CL o..szapc o..sz.pc .....a.. Shift
D4 0A AAM AL AH o..szapc ...sz.p. o....a.c ASCII Adjust AX After Multiply
D4 AMX AL AH imm8 o..szapc ...sz.p. o....a.c Adjust AX After Multiply
D5 0A AAD AL AH o..szapc ...sz.p. o....a.c ASCII Adjust AX Before Division
D5 ADX AL AH imm8 o..szapc ...sz.p. o....a.c Adjust AX Before Division
D6 02+ D2 undefined Undefined and Reserved; Does not Generate #UD
D6 02+ U3 SALC AL .......c Set AL If Carry
SETALC AL
D7 XLAT AL m8 Table Look-up Translation
XLATB AL m8
D8 0 FADD ST m32real 0123 .1.. 0.23 Add
FADD ST STi
D8 1 FMUL ST m32real 0123 .1.. 0.23 Multiply
FMUL ST STi
D8 2 FCOM ST STi/m32real 0123 0123 Compare Real
D8 D1 2 FCOM ST ST1 0123 0123 Compare Real
D8 3 p FCOMP ST STi/m32real 0123 0123 Compare Real and Pop
D8 D9 3 p FCOMP ST ST1 0123 0123 Compare Real and Pop
D8 4 FSUB ST m32real 0123 .1.. 0.23 Subtract
FSUB ST STi
D8 5 FSUBR ST m32real 0123 .1.. 0.23 Reverse Subtract
FSUBR ST STi
D8 6 FDIV ST m32real 0123 .1.. 0.23 Divide
FDIV ST STi
D8 7 FDIVR ST m32real 0123 .1.. 0.23 Reverse Divide
FDIVR ST STi
D9 0 s FLD ST STi/m32real 0123 .1.. 0.23 Load Floating Point Value
D9 1 FXCH ST STi 0123 .1.. 0.23 Exchange Register Contents
D9 C9 1 FXCH ST ST1 0123 .1.. 0.23 Exchange Register Contents
D9 2 FST m32real ST 0123 .1.. 0.23 Store Floating Point Value
D9 D0 2 FNOP 0123 0123 No Operation
D9 3 p FSTP m32real ST 0123 .1.. 0.23 Store Floating Point Value and Pop
D9 3 03+ U7 p FSTP1 STi ST 0123 .1.. 0.23 Store Floating Point Value and Pop
D9 4 FLDENV m14/28 0123 0123 Load x87 FPU Environment
D9 E0 4 FCHS ST 0123 .1.. 0.23 Change Sign
D9 E1 4 FABS ST 0123 .1.. 0.23 Absolute Value
D9 E4 4 FTST ST 0123 0123 Test
D9 E5 4 FXAM ST 0123 0123 Examine
D9 5 FLDCW m16 0123 0123 Load x87 FPU Control Word
D9 E8 5 s FLD1 ST 0123 .1.. 0.23 Load Constant +1.0
D9 E9 5 s FLDL2T ST 0123 .1.. 0.23 Load Constant log210
D9 EA 5 s FLDL2E ST 0123 .1.. 0.23 Load Constant log2e
D9 EB 5 s FLDPI ST 0123 .1.. 0.23 Load Constant π
D9 EC 5 s FLDLG2 ST 0123 .1.. 0.23 Load Constant log102
D9 ED 5 s FLDLN2 ST 0123 .1.. 0.23 Load Constant loge2
D9 EE 5 s FLDZ ST 0123 .1.. 0.23 Load Constant +0.0
D9 6 FNSTENV m14/28 0123 0123 Store x87 FPU Environment
9B D9 6 FSTENV m14/28 0123 0123 Store x87 FPU Environment
D9 F0 6 F2XM1 ST 0123 .1.. 0.23 Compute 2x-1
D9 F1 6 p FYL2X ST1 ST 0123 .1.. 0.23 Compute y × log2x and Pop
D9 F2 6 s FPTAN ST 0123 .12. 0..3 Partial Tangent
D9 F3 6 p FPATAN ST1 ST 0123 .1.. 0.23 Partial Arctangent and Pop
D9 F4 6 s FXTRACT ST 0123 .1.. 0.23 Extract Exponent and Significand
D9 F5 6 FPREM1 ST ST1 0123 0123 IEEE Partial Remainder
D9 F6 6 FDECSTP 0123 .1.. 0.23 .0.. Decrement Stack-Top Pointer
D9 F7 6 FINCSTP 0123 .1.. 0.23 .0.. Increment Stack-Top Pointer
D9 7 FNSTCW m16 0123 0123 Store x87 FPU Control Word
9B D9 7 FSTCW m16 0123 0123 Store x87 FPU Control Word
D9 F8 7 FPREM ST ST1 0123 0123 Partial Remainder (for compatibility with i8087 and i287)
D9 F9 7 p FYL2XP1 ST1 ST 0123 .1.. 0.23 Compute y × log2(x+1) and Pop
D9 FA 7 FSQRT ST 0123 .1.. 0.23 Square Root
D9 FB 7 s FSINCOS ST 0123 .12. 0..3 Sine and Cosine
D9 FC 7 FRNDINT ST 0123 .1.. 0.23 Round to Integer
D9 FD 7 FSCALE ST ST1 0123 .1.. 0.23 Scale
D9 FE 7 FSIN ST 0123 .12. 0..3 Sine
D9 FF 7 FCOS ST 0123 .12. 0..3 Cosine
DA 0 FIADD ST m32int 0123 .1.. 0.23 Add
DA 0 PP+ FCMOVB ST STi .......c 0123 .1.. 0.23 Floating-Point Conditional Move - below (CF=1)
DA 1 FIMUL ST m32int 0123 .1.. 0.23 Multiply
DA 1 PP+ FCMOVE ST STi ....z... 0123 .1.. 0.23 Floating-Point Conditional Move - equal (ZF=1)
DA 2 FICOM ST m32int 0123 0123 Compare Integer
DA 2 PP+ FCMOVBE ST STi ....z... 0123 .1.. 0.23 Floating-Point Conditional Move - below or equal (CF=1 or ZF=1)
DA 3 p FICOMP ST m32int 0123 0123 Compare Integer and Pop
DA 3 PP+ FCMOVU ST STi ......p. 0123 .1.. 0.23 Floating-Point Conditional Move - unordered (PF=1)
DA 4 FISUB ST m32int 0123 .1.. 0.23 Subtract
DA 5 FISUBR ST m32int 0123 .1.. 0.23 Reverse Subtract
DA E9 5 03+ P FUCOMPP ST ST1 0123 0123 Unordered Compare Floating Point Values and Pop Twice
DA 6 FIDIV ST m32int 0123 .1.. 0.23 Divide
DA 7 FIDIVR ST m32int 0123 .1.. 0.23 Reverse Divide
DB 0 s FILD ST m32int 0123 .1.. 0.23 Load Integer
DB 0 PP+ FCMOVNB ST STi .......c 0123 .1.. 0.23 Floating-Point Conditional Move - not below (CF=0)
DB 1 P4++ p FISTTP m32int ST sse3 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
DB 1 PP+ FCMOVNE ST STi ....z... 0123 .1.. 0.23 Floating-Point Conditional Move - not equal (ZF=0)
DB 2 FIST m32int ST 0123 .1.. 0.23 Store Integer
DB 2 PP+ FCMOVNBE ST STi ....z... 0123 .1.. 0.23 Floating-Point Conditional Move - below or equal (CF=0 and ZF=0)
DB 3 p FISTP m32int ST 0123 .1.. 0.23 Store Integer and Pop
DB 3 PP+ FCMOVNU ST STi ......p. 0123 .1.. 0.23 Floating-Point Conditional Move - not unordered (PF=0)
DB E0 4 01+ D4 FNENI nop Treated as Integer NOP
DB E1 4 01+ D4 FNDISI nop Treated as Integer NOP
DB E2 4 FNCLEX 0123 0123 Clear Exceptions
9B DB E2 4 FCLEX 0123 0123 Clear Exceptions
DB E3 4 FNINIT 0123 0000 Initialize Floating-Point Unit
9B DB E3 4 FINIT 0123 0000 Initialize Floating-Point Unit
DB E4 4 03+ D5 FNSETPM nop Treated as Integer NOP
DB 5 s FLD ST m80real 0123 .1.. 0.23 Load Floating Point Value
DB 5 PP+ FUCOMI ST STi o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS
DB 6 PP+ FCOMI ST STi o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS
DB 7 p FSTP m80real ST 0123 .1.. 0.23 Store Floating Point Value and Pop
DC 0 FADD ST m64real 0123 .1.. 0.23 Add
DC 0 FADD STi ST 0123 .1.. 0.23 Add
DC 1 FMUL ST m64real 0123 .1.. 0.23 Multiply
DC 1 FMUL STi ST 0123 .1.. 0.23 Multiply
DC 2 FCOM ST m64real 0123 0123 Compare Real
DC 2 03+ U7 FCOM2 ST STi 0123 0123 Compare Real
DC 3 p FCOMP ST m64real 0123 0123 Compare Real and Pop
DC 3 03+ U7 p FCOMP3 ST STi 0123 0123 Compare Real and Pop
DC 4 FSUB ST m64real 0123 .1.. 0.23 Subtract
DC 4 FSUBR STi ST 0123 .1.. 0.23 Reverse Subtract
DC 5 FSUBR ST m64real 0123 .1.. 0.23 Reverse Subtract
DC 5 FSUB STi ST 0123 .1.. 0.23 Subtract
DC 6 FDIV ST m64real 0123 .1.. 0.23 Divide
DC 6 FDIVR STi ST 0123 .1.. 0.23 Reverse Divide
DC 7 FDIVR ST m64real 0123 .1.. 0.23 Reverse Divide
DC 7 FDIV STi ST 0123 .1.. 0.23 Divide and Pop
DD 0 s FLD ST m64real 0123 .1.. 0.23 Load Floating Point Value
DD 0 FFREE STi 0123 0123 Free Floating-Point Register
DD 1 P4++ p FISTTP m64int ST sse3 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
DD 1 03+ U7 FXCH4 ST STi 0123 .1.. 0.23 Exchange Register Contents
DD 2 FST m64real ST 0123 .1.. 0.23 Store Floating Point Value
DD 2 FST ST STi 0123 .1.. 0.23 Store Floating Point Value
DD 3 p FSTP m64real ST 0123 .1.. 0.23 Store Floating Point Value and Pop
DD 3 p FSTP ST STi 0123 .1.. 0.23 Store Floating Point Value and Pop
DD 4 FRSTOR ST ST1 ST2 ... 0123 0123 Restore x87 FPU State
DD 4 03+ FUCOM ST STi 0123 0123 Unordered Compare Floating Point Values
DD E1 4 03+ FUCOM ST ST1 0123 0123 Unordered Compare Floating Point Values
DD 5 03+ p FUCOMP ST STi 0123 0123 Unordered Compare Floating Point Values and Pop
DD E9 5 03+ p FUCOMP ST ST1 0123 0123 Unordered Compare Floating Point Values and Pop
DD 6 FNSAVE m94/108 ST ST1 ... 0123 0123 0000 Store x87 FPU State
9B DD 6 FSAVE m94/108 ST ST1 ... 0123 0123 0000 Store x87 FPU State
DD 7 FNSTSW m16 0123 0123 Store x87 FPU Status Word
9B DD 7 FSTSW m16 0123 0123 Store x87 FPU Status Word
DE 0 FIADD ST m16int 0123 .1.. 0.23 Add
DE 0 p FADDP STi ST 0123 .1.. 0.23 Add and Pop
DE C1 0 p FADDP ST1 ST 0123 .1.. 0.23 Add and Pop
DE 1 FIMUL ST m16int 0123 .1.. 0.23 Multiply
DE 1 p FMULP STi ST 0123 .1.. 0.23 Multiply and Pop
DE C9 1 p FMULP ST1 ST 0123 .1.. 0.23 Multiply and Pop
DE 2 FICOM ST m16int 0123 0123 Compare Integer
DE 2 03+ U7 p FCOMP5 ST STi 0123 0123 Compare Real and Pop
DE 3 p FICOMP ST m16int 0123 0123 Compare Integer and Pop
DE D9 3 P FCOMPP ST ST1 0123 0123 Compare Real and Pop Twice
DE 4 FISUB ST m16int 0123 .1.. 0.23 Subtract
DE 4 p FSUBRP STi ST 0123 .1.. 0.23 Reverse Subtract and Pop
DE E1 4 p FSUBRP ST1 ST 0123 .1.. 0.23 Reverse Subtract and Pop
DE 5 FISUBR ST m16int 0123 .1.. 0.23 Reverse Subtract
DE 5 p FSUBP STi ST 0123 .1.. 0.23 Subtract and Pop
DE E9 5 p FSUBP ST1 ST 0123 .1.. 0.23 Subtract and Pop
DE 6 FIDIV ST m16int 0123 .1.. 0.23 Divide
DE 6 p FDIVRP STi ST 0123 .1.. 0.23 Reverse Divide and Pop
DE F1 6 p FDIVRP ST1 ST 0123 .1.. 0.23 Reverse Divide and Pop
DE 7 FIDIVR ST m16int 0123 .1.. 0.23 Reverse Divide
DE 7 p FDIVP STi ST 0123 .1.. 0.23 Divide and Pop
DE F9 7 p FDIVP ST1 ST 0123 .1.. 0.23 Divide and Pop
DF 0 s FILD ST m16int 0123 .1.. 0.23 Load Integer
DF 0 D6 p FFREEP STi 0123 0123 Free Floating-Point Register and Pop
DF 1 P4++ p FISTTP m16int ST sse3 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
DF 1 03+ U7 FXCH7 ST STi 0123 .1.. 0.23 Exchange Register Contents
DF 2 FIST m16int ST 0123 .1.. 0.23 Store Integer
DF 2 03+ U7 p FSTP8 STi ST 0123 .1.. 0.23 Store Floating Point Value and Pop
DF 3 p FISTP m16int ST 0123 .1.. 0.23 Store Integer and Pop
DF 3 03+ U7 p FSTP9 STi ST 0123 .1.. 0.23 Store Floating Point Value and Pop
DF 4 s FBLD ST m80dec 0123 .1.. 0.23 Load Binary Coded Decimal
DF E0 4 02+ FNSTSW AX 0123 0123 Store x87 FPU Status Word
9B DF E0 4 02+ FSTSW AX 0123 0123 Store x87 FPU Status Word
DF 5 s FILD ST m64int 0123 .1.. 0.23 Load Integer
DF 5 PP+ p FUCOMIP ST STi o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS and Pop
DF 6 p FBSTP m80dec ST 0123 .1.. 0.23 Store BCD Integer and Pop
DF 6 PP+ p FCOMIP ST STi o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS and Pop
DF 7 p FISTP m64int ST 0123 .1.. 0.23 Store Integer and Pop
E0 LOOPNZ eCX rel8 ....z... Decrement count; Jump short if count!=0 and ZF=0
LOOPNE eCX rel8
E1 LOOPZ eCX rel8 ....z... Decrement count; Jump short if count!=0 and ZF=1
LOOPE eCX rel8
E2 LOOP eCX rel8 Decrement count; Jump short if count!=0
E3 JCXZ rel8 CX Jump short if eCX register is 0
JECXZ rel8 ECX
E4 f1 IN AL imm8 Input from Port
E5 f1 IN eAX imm8 Input from Port
E6 f1 OUT imm8 AL Output to Port
E7 f1 OUT imm8 eAX Output to Port
E8 CALL rel16/32 Call Procedure
E9 JMP rel16/32 Jump
EA JMPF ptr16:16/32 Jump
EB JMP rel8 Jump
EC f1 IN AL DX Input from Port
ED f1 IN eAX DX Input from Port
EE f1 OUT DX AL Output to Port
EF f1 OUT DX eAX Output to Port
F0 LOCK Assert LOCK# Signal Prefix
F1 D2 undefined Undefined and Reserved; Does not Generate #UD
F1 03+ U8 INT1 eFlags ..i..... ..i..... ..i..... Call to Interrupt Procedure
ICEBP eFlags
F2 REPNZ eCX ....z... Repeat String Operation Prefix
REPNE eCX
F2 U REP eCX Repeat String Operation Prefix
F2 P4+ M no mnemonic sse2 Scalar Double-precision Prefix
F3 REPZ eCX ....z... Repeat String Operation Prefix
REPE eCX
F3 REP eCX Repeat String Operation Prefix
F3 P3+ M no mnemonic sse1 Scalar Single-precision Prefix
F4 0 HLT Halt
F5 CMC .......c .......c .......c Complement Carry Flag
F6 0 TEST r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Compare
F6 1 U9 TEST r/m8 imm8 o..szapc o..sz.pc .....a.. o......c Logical Compare
F6 2 NOT r/m8 One's Complement Negation
F6 3 NEG r/m8 o..szapc o..szapc Two's Complement Negation
F6 4 MUL AX AL r/m8 o..szapc o......c ...szap. Unsigned Multiply
F6 5 IMUL AX AL r/m8 o..szapc o......c ...szap. Signed Multiply
F6 6 DIV AL AH AX r/m8 o..szapc o..szapc Unsigned Divide
F6 7 IDIV AL AH AX r/m8 o..szapc o..szapc Signed Divide
F7 0 TEST r/m16/32 imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Compare
F7 1 U9 TEST r/m16/32 imm16/32 o..szapc o..sz.pc .....a.. o......c Logical Compare
F7 2 NOT r/m16/32 One's Complement Negation
F7 3 NEG r/m16/32 o..szapc o..szapc Two's Complement Negation
F7 4 MUL eDX eAX r/m16/32 o..szapc o......c ...szap. Unsigned Multiply
F7 5 IMUL eDX eAX r/m16/32 o..szapc o......c ...szap. Signed Multiply
F7 6 DIV eDX eAX r/m16/32 o..szapc o..szapc Unsigned Divide
F7 7 IDIV eDX eAX r/m16/32 o..szapc o..szapc Signed Divide
F8 CLC .......c .......c .......c Clear Carry Flag
F9 STC .......c .......c .......C Set Carry Flag
FA f1 CLI ..i..... ..i..... ..i..... Clear Interrupt Flag
FB f1 STI ..i..... ..i..... ..I..... Set Interrupt Flag
FC CLD .d...... .d...... .d...... Clear Direction Flag
FD STD .d...... .d...... .D...... Set Direction Flag
FE 0 INC r/m8 o..szap. o..szap. Increment by 1
FE 1 DEC r/m8 o..szap. o..szap. Decrement by 1
FF 0 INC r/m16/32 o..szap. o..szap. Increment by 1
FF 1 DEC r/m16/32 o..szap. o..szap. Decrement by 1
FF 2 CALL r/m16/32 Call Procedure
FF 3 CALLF m16:16/32 Call Procedure
FF 4 JMP r/m16/32 Jump
FF 5 JMPF m16:16/32 Jump
FF 6 PUSH r/m16/32 Push Word, Doubleword or Quadword Onto the Stack
pf 0F po so o proc st m rl x mnemonic op1 op2 op3 op4 iext tested f modif f def f undef f f values description, notes                                                  
0F 00 0 02+ P SLDT m16 LDTR Store Local Descriptor Table Register
SLDT r16/32 LDTR
0F 00 1 02+ P STR m16 TR Store Task Register
STR r16/32 TR
0F 00 2 02+ P 0 LLDT LDTR r/m16 Load Local Descriptor Table Register
0F 00 3 02+ P 0 LTR TR r/m16 Load Task Register
0F 00 4 02+ P VERR r/m16 ....z... ....z... Verify a Segment for Reading
0F 00 5 02+ P VERW r/m16 ....z... ....z... Verify a Segment for Writing
0F 01 0 02+ SGDT m GDTR Store Global Descriptor Table Register
0F 01 1 02+ SIDT m IDTR Store Interrupt Descriptor Table Register
0F 01 C8 1 P4++ 0 MONITOR m8 ECX EDX sse3 Set Up Monitor Address
0F 01 C9 1 P4++ 0 MWAIT EAX ECX sse3 Monitor Wait
0F 01 2 02+ 0 LGDT GDTR m Load Global Descriptor Table Register
0F 01 3 02+ 0 LIDT IDTR m Load Interrupt Descriptor Table Register
0F 01 4 02+ SMSW m16 MSW Store Machine Status Word
SMSW r16/32 MSW
0F 01 6 02+ LMSW MSW r/m16 Load Machine Status Word
0F 01 7 04+ 0 INVLPG m Invalidate TLB Entry
0F 02 r 02+ P LAR r16/32 m16 ....z... ....z... Load Access Rights Byte
LAR r16/32 r16/32
0F 03 r 02+ P LSL r16/32 m16 ....z... ....z... Load Segment Limit
LSL r16/32 r16/32
0F 06 02+ 0 CLTS CR0 Clear Task-Switched Flag in CR0
0F 08 04+ 0 INVD Invalidate Internal Caches
0F 09 04+ 0 WBINVD Write Back and Invalidate Cache
0F 0B 02+ UD2 Undefined Instruction
0F 0D PP+ M10 NOP r/m16/32 No Operation
0F 10 r P3+ MOVUPS xmm xmm/m128 sse1 Move Unaligned Packed Single-FP Values
F3 0F 10 r P3+ MOVSS xmm xmm/m32 sse1 Move Scalar Single-FP Values
66 0F 10 r P4+ MOVUPD xmm xmm/m128 sse2 Move Unaligned Packed Double-FP Value
F2 0F 10 r P4+ MOVSD xmm xmm/m64 sse2 Move Scalar Double-FP Value
0F 11 r P3+ MOVUPS xmm/m128 xmm sse1 Move Unaligned Packed Single-FP Values
F3 0F 11 r P3+ MOVSS xmm/m32 xmm sse1 Move Scalar Single-FP Values
66 0F 11 r P4+ MOVUPD xmm/m128 xmm sse2 Move Unaligned Packed Double-FP Values
F2 0F 11 r P4+ MOVSD xmm/m64 xmm sse2 Move Scalar Double-FP Value
0F 12 r P3+ MOVHLPS xmm xmm sse1 Move Packed Single-FP Values High to Low
0F 12 r P3+ MOVLPS xmm m64 sse1 Move Low Packed Single-FP Values
66 0F 12 r P4+ MOVLPD xmm m64 sse2 Move Low Packed Double-FP Value
F2 0F 12 r P4++ MOVDDUP xmm xmm/m64 sse3 Move One Double-FP and Duplicate
F3 0F 12 r P4++ MOVSLDUP xmm xmm/m64 sse3 Move Packed Single-FP Low and Duplicate
0F 13 r P3+ MOVLPS m64 xmm sse1 Move Low Packed Single-FP Values
66 0F 13 r P4+ MOVLPD m64 xmm sse2 Move Low Packed Double-FP Value
0F 14 r P3+ UNPCKLPS xmm xmm/m64 sse1 Unpack and Interleave Low Packed Single-FP Values
66 0F 14 r P4+ UNPCKLPD xmm xmm/m128 sse2 Unpack and Interleave Low Packed Double-FP Values
0F 15 r P3+ UNPCKHPS xmm xmm/m64 sse1 Unpack and Interleave High Packed Single-FP Values
66 0F 15 r P4+ UNPCKHPD xmm xmm/m128 sse2 Unpack and Interleave High Packed Double-FP Values
0F 16 r P3+ MOVLHPS xmm xmm sse1 Move Packed Single-FP Values Low to High
0F 16 r P3+ MOVHPS xmm m64 sse1 Move High Packed Single-FP Values
66 0F 16 r P4+ MOVHPD xmm m64 sse2 Move High Packed Double-FP Value
F3 0F 16 r P4++ MOVSHDUP xmm xmm/m64 sse3 Move Packed Single-FP High and Duplicate
0F 17 r P3+ MOVHPS m64 xmm sse1 Move High Packed Single-FP Values
66 0F 17 r P4+ MOVHPD m64 xmm sse2 Move High Packed Double-FP Value
0F 18 0 P3+ PREFETCHNTA m8 sse1 Prefetch Data Into Caches
0F 18 1 P3+ PREFETCHT0 m8 sse1 Prefetch Data Into Caches
0F 18 2 P3+ PREFETCHT1 m8 sse1 Prefetch Data Into Caches
0F 18 3 P3+ PREFETCHT2 m8 sse1 Prefetch Data Into Caches
0F 1F P4++ NOP r/m16/32 No Operation
0F 20 r 03+ 0 MOV r32 CRn o..szapc o..szapc Move to/from Control Registers
0F 20 r 03+ U11 0 MOV r32 CRn o..szapc o..szapc Move to/from Control Registers
0F 21 r 03+ 0 MOV r32 DRn o..szapc o..szapc Move to/from Debug Registers
0F 21 r 03+ U11 0 MOV r32 DRn o..szapc o..szapc Move to/from Debug Registers
0F 22 r 03+ 0 MOV CRn r32 o..szapc o..szapc Move to/from Control Registers
0F 22 r 03+ U11 0 MOV CRn r32 o..szapc o..szapc Move to/from Control Registers
0F 23 r 03+ 0 MOV DRn r32 o..szapc o..szapc Move to/from Debug Registers
0F 23 r 03+ U11 0 MOV DRn r64 o..szapc o..szapc Move to/from Debug Registers
0F 28 r P3+ MOVAPS xmm xmm/m128 sse1 Move Aligned Packed Single-FP Values
66 0F 28 r P4+ MOVAPD xmm xmm/m128 sse2 Move Aligned Packed Double-FP Values
0F 29 r P3+ MOVAPS xmm/m128 xmm sse1 Move Aligned Packed Single-FP Values
66 0F 29 r P4+ MOVAPD xmm/m128 xmm sse2 Move Aligned Packed Double-FP Values
0F 2A r P3+ CVTPI2PS xmm mm/m64 sse1 Convert Packed DW Integers to Packed Single-FP Values
F3 0F 2A r P3+ CVTSI2SS xmm r/m32 sse1 Convert DW Integer to Scalar Single-FP Value
66 0F 2A r P4+ CVTPI2PD xmm mm/m64 sse2 Convert Packed DW Integers to Packed Double-FP Values
F2 0F 2A r P4+ CVTSI2SD xmm r/m32 sse2 Convert DW Integer to Scalar Double-FP Value
0F 2B r P3+ MOVNTPS m128 xmm sse1 Store Packed Single-FP Values Using Non-Temporal Hint
66 0F 2B r P4+ MOVNTPD m128 xmm sse2 Store Packed Double-FP Values Using Non-Temporal Hint
0F 2C r P3+ CVTTPS2PI mm xmm/m64 sse1 Convert with Trunc. Packed Single-FP Values to Packed DW Integers
F3 0F 2C r P3+ CVTTSS2SI r32 xmm/m32 sse1 Convert with Trunc. Scalar Single-FP Value to DW Integer
66 0F 2C r P4+ CVTTPD2PI mm xmm/m128 sse2 Convert with Trunc. Packed Double-FP Values to Packed DW Integers
F2 0F 2C r P4+ CVTTSD2SI r32 xmm/m64 sse2 Convert with Trunc. Scalar Double-FP Value to Signed DW Integer
0F 2D r P3+ CVTPS2PI mm xmm/m64 sse1 Convert Packed Single-FP Values to Packed DW Integers
F3 0F 2D r P3+ CVTSS2SI r32 xmm/m32 sse1 Convert Scalar Single-FP Value to DW Integer
66 0F 2D r P4+ CVTPD2PI mm xmm/m128 sse2 Convert Packed Double-FP Values to Packed DW Integers
F2 0F 2D r P4+ CVTSD2SI r32 xmm/m64 sse2 Convert Scalar Double-FP Value to DW Integer
0F 2E r P3+ UCOMISS xmm xmm/m32 sse1 ....z.pc ....z.pc Unordered Compare Scalar Single-FP Values and Set EFLAGS
66 0F 2E r P4+ UCOMISD xmm xmm/m64 sse2 ....z.pc ....z.pc Unordered Compare Scalar Double-FP Values and Set EFLAGS
0F 2F r P3+ COMISS xmm xmm/m32 sse1 ....z.pc ....z.pc Compare Scalar Ordered Single-FP Values and Set EFLAGS
66 0F 2F r P4+ COMISD xmm xmm/m64 sse2 ....z.pc ....z.pc Compare Scalar Ordered Double-FP Values and Set EFLAGS
0F 30 P1+ 0 WRMSR MSR eCX eAX eDX Write to Model Specific Register
0F 31 P1+ f2 RDTSC EAX EDX IA32_T... Read Time-Stamp Counter
0F 32 P1+ 0 RDMSR eAX eDX eCX MSR Read from Model Specific Register
0F 33 PX+ f3 RDPMC EAX EDX PMC Read Performance-Monitoring Counters
0F 34 P2+ P SYSENTER SS ESP IA32_S... ... ..i..... ..i..... ..i..... Fast System Call
0F 35 P2+ P 0 SYSEXIT SS eSP IA32_S... ... Fast Return from Fast System Call
0F 38 00 r C2+ PSHUFB mm mm/m64 ssse3 Packed Shuffle Bytes
66 0F 38 00 r C2+ PSHUFB xmm xmm/m128 ssse3 Packed Shuffle Bytes
0F 38 01 r C2+ PHADDW mm mm/m64 ssse3 Packed Horizontal Add
66 0F 38 01 r C2+ PHADDW xmm xmm/m128 ssse3 Packed Horizontal Add
0F 38 02 r C2+ PHADDD mm mm/m64 ssse3 Packed Horizontal Add
66 0F 38 02 r C2+ PHADDD xmm xmm/m128 ssse3 Packed Horizontal Add
0F 38 03 r C2+ PHADDSW mm mm/m64 ssse3 Packed Horizontal Add and Saturate
66 0F 38 03 r C2+ PHADDSW xmm xmm/m128 ssse3 Packed Horizontal Add and Saturate
0F 38 04 r C2+ PMADDUBSW mm mm/m64 ssse3 Multiply and Add Packed Signed and Unsigned Bytes
66 0F 38 04 r C2+ PMADDUBSW xmm xmm/m128 ssse3 Multiply and Add Packed Signed and Unsigned Bytes
0F 38 05 r C2+ PHSUBW mm mm/m64 ssse3 Packed Horizontal Subtract
66 0F 38 05 r C2+ PHSUBW xmm xmm/m128 ssse3 Packed Horizontal Subtract
0F 38 06 r C2+ PHSUBD mm mm/m64 ssse3 Packed Horizontal Subtract
66 0F 38 06 r C2+ PHSUBD xmm xmm/m128 ssse3 Packed Horizontal Subtract
0F 38 07 r C2+ PHSUBSW mm mm/m64 ssse3 Packed Horizontal Subtract and Saturate
66 0F 38 07 r C2+ PHSUBSW xmm xmm/m128 ssse3 Packed Horizontal Subtract and Saturate
0F 38 08 r C2+ PSIGNB mm mm/m64 ssse3 Packed SIGN
66 0F 38 08 r C2+ PSIGNB xmm xmm/m128 ssse3 Packed SIGN
0F 38 09 r C2+ PSIGNW mm mm/m64 ssse3 Packed SIGN
66 0F 38 09 r C2+ PSIGNW xmm xmm/m128 ssse3 Packed SIGN
0F 38 0A r C2+ PSIGND mm mm/m64 ssse3 Packed SIGN
66 0F 38 0A r C2+ PSIGND xmm xmm/m128 ssse3 Packed SIGN
0F 38 0B r C2+ PMULHRSW mm mm/m64 ssse3 Packed Multiply High with Round and Scale
66 0F 38 0B r C2+ PMULHRSW xmm xmm/m128 ssse3 Packed Multiply High with Round and Scale
0F 38 1C r C2+ PABSB mm mm/m64 ssse3 Packed Absolute Value
66 0F 38 1C r C2+ PABSB xmm xmm/m128 ssse3 Packed Absolute Value
0F 38 1D r C2+ PABSW mm mm/m64 ssse3 Packed Absolute Value
66 0F 38 1D r C2+ PABSW xmm xmm/m128 ssse3 Packed Absolute Value
0F 38 1E r C2+ PABSD mm mm/m64 ssse3 Packed Absolute Value
66 0F 38 1E r C2+ PABSD xmm xmm/m128 ssse3 Packed Absolute Value
0F 3A 0F r C2+ PALIGNR mm mm/m64 ssse3 Packed Align Right
66 0F 3A 0F r C2+ PALIGNR xmm xmm/m128 ssse3 Packed Align Right
0F 40 r PP+ CMOVO r16/32 r/m16/32 o....... Conditional Move - overflow (OF=1)
0F 41 r PP+ CMOVNO r16/32 r/m16/32 o....... Conditional Move - not overflow (OF=0)
0F 42 r PP+ CMOVB r16/32 r/m16/32 .......c Conditional Move - below/not above or equal/carry (CF=1)
CMOVNAE r16/32 r/m16/32
CMOVC r16/32 r/m16/32
0F 43 r PP+ CMOVNB r16/32 r/m16/32 .......c Conditional Move - not below/above or equal/not carry (CF=0)
CMOVAE r16/32 r/m16/32
CMOVNC r16/32 r/m16/32
0F 44 r PP+ CMOVZ r16/32 r/m16/32 ....z... Conditional Move - zero/equal (ZF=0)
CMOVE r16/32 r/m16/32
0F 45 r PP+ CMOVNZ r16/32 r/m16/32 ....z... Conditional Move - not zero/not equal (ZF=1)
CMOVNE r16/32 r/m16/32
0F 46 r PP+ CMOVBE r16/32 r/m16/32 ....z..c Conditional Move - below or equal/not above (CF=1 AND ZF=1)
CMOVNA r16/32 r/m16/32
0F 47 r PP+ CMOVNBE r16/32 r/m16/32 ....z..c Conditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVA r16/32 r/m16/32
0F 48 r PP+ CMOVS r16/32 r/m16/32 ...s.... Conditional Move - sign (SF=1)
0F 49 r PP+ CMOVNS r16/32 r/m16/32 ...s.... Conditional Move - not sign (SF=0)
0F 4A r PP+ CMOVP r16/32 r/m16/32 ......p. Conditional Move - parity/parity even (PF=1)
CMOVPE r16/32 r/m16/32
0F 4B r PP+ CMOVNP r16/32 r/m16/32 ......p. Conditional Move - not parity/parity odd
CMOVPO r16/32 r/m16/32
0F 4C r PP+ CMOVL r16/32 r/m16/32 o..s.... Conditional Move - less/not greater (SF!=OF)
CMOVNGE r16/32 r/m16/32
0F 4D r PP+ CMOVNL r16/32 r/m16/32 o..s.... Conditional Move - not less/greater or equal (SF=OF)
CMOVGE r16/32 r/m16/32
0F 4E r PP+ CMOVLE r16/32 r/m16/32 o..sz... Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNG r16/32 r/m16/32
0F 4F r PP+ CMOVNLE r16/32 r/m16/32 o..sz... Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVG r16/32 r/m16/32
0F 50 r P3+ MOVMSKPS r32 xmm sse1 Extract Packed Single-FP Sign Mask
66 0F 50 r P4+ MOVMSKPD r32 xmm sse2 Extract Packed Double-FP Sign Mask
0F 51 r P3+ SQRTPS xmm xmm/m128 sse1 Compute Square Roots of Packed Single-FP Values
F3 0F 51 r P3+ SQRTSS xmm xmm/m32 sse1 Compute Square Root of Scalar Single-FP Value
66 0F 51 r P4+ SQRTPD xmm xmm/m128 sse2 Compute Square Roots of Packed Double-FP Values
F2 0F 51 r P4+ SQRTSD xmm xmm/m64 sse2 Compute Square Root of Scalar Double-FP Value
0F 52 r P3+ RSQRTPS xmm xmm/m128 sse1 Compute Reciprocals of Square Roots of Packed Single-FP Values
F3 0F 52 r P3+ RSQRTSS xmm xmm/m32 sse1 Compute Reciprocal of Square Root of Scalar Single-FP Value
0F 53 r P3+ RCPPS xmm xmm/m128 sse1 Compute Reciprocals of Packed Single-FP Values
F3 0F 53 r P3+ RCPSS xmm xmm/m32 sse1 Compute Reciprocal of Scalar Single-FP Values
0F 54 r P3+ ANDPS xmm xmm/m128 sse1 Bitwise Logical AND of Packed Single-FP Values
66 0F 54 r P4+ ANDPD xmm xmm/m128 sse2 Bitwise Logical AND of Packed Double-FP Values
0F 55 r P3+ ANDNPS xmm xmm/m128 sse1 Bitwise Logical AND NOT of Packed Single-FP Values
66 0F 55 r P4+ ANDNPD xmm xmm/m128 sse2 Bitwise Logical AND NOT of Packed Double-FP Values
0F 56 r P3+ ORPS xmm xmm/m128 sse1 Bitwise Logical OR of Single-FP Values
66 0F 56 r P4+ ORPD xmm xmm/m128 sse2 Bitwise Logical OR of Double-FP Values
0F 57 r P3+ XORPS xmm xmm/m128 sse1 Bitwise Logical XOR for Single-FP Values
66 0F 57 r P4+ XORPD xmm xmm/m128 sse2 Bitwise Logical XOR for Double-FP Values
0F 58 r P3+ ADDPS xmm xmm/m128 sse1 Add Packed Single-FP Values
F3 0F 58 r P3+ ADDSS xmm xmm/m32 sse1 Add Scalar Single-FP Values
66 0F 58 r P4+ ADDPD xmm xmm/m128 sse2 Add Packed Double-FP Values
F2 0F 58 r P4+ ADDSD xmm xmm/m64 sse2 Add Scalar Double-FP Values
0F 59 r P3+ MULPS xmm xmm/m128 sse1 Multiply Packed Single-FP Values
F3 0F 59 r P3+ MULSS xmm xmm/m32 sse1 Multiply Scalar Single-FP Value
66 0F 59 r P4+ MULPD xmm xmm/m128 sse2 Multiply Packed Double-FP Values
F2 0F 59 r P4+ MULSD xmm xmm/m64 sse2 Multiply Scalar Double-FP Values
0F 5A r P4+ CVTPS2PD xmm xmm/m128 sse2 Convert Packed Single-FP Values to Packed Double-FP Values
66 0F 5A r P4+ CVTPD2PS xmm xmm/m128 sse2 Convert Packed Double-FP Values to Packed Single-FP Values
F3 0F 5A r P4+ CVTSS2SD xmm xmm/m32 sse2 Convert Scalar Single-FP Value to Scalar Double-FP Value
F2 0F 5A r P4+ CVTSD2SS xmm xmm/m64 sse2 Convert Scalar Double-FP Value to Scalar Single-FP Value
0F 5B r P4+ CVTDQ2PS xmm xmm/m128 sse2 Convert Packed DW Integers to Packed Single-FP Values
66 0F 5B r P4+ CVTPS2DQ xmm xmm/m128 sse2 Convert Packed Single-FP Values to Packed DW Integers
F3 0F 5B r P4+ CVTTPS2DQ xmm xmm/m128 sse2 Convert with Trunc. Packed Single-FP Values to Packed DW Integers
0F 5C r P3+ SUBPS xmm xmm/m128 sse1 Subtract Packed Single-FP Values
F3 0F 5C r P3+ SUBSS xmm xmm/m32 sse1 Subtract Scalar Single-FP Values
66 0F 5C r P4+ SUBPD xmm xmm/m128 sse2 Subtract Packed Double-FP Values
F2 0F 5C r P4+ SUBSD xmm xmm/m64 sse2 Subtract Scalar Double-FP Values
0F 5D r P3+ MINPS xmm xmm/m128 sse1 Return Minimum Packed Single-FP Values
F3 0F 5D r P3+ MINSS xmm xmm/m32 sse1 Return Minimum Scalar Single-FP Value
66 0F 5D r P4+ MINPD xmm xmm/m128 sse2 Return Minimum Packed Double-FP Values
F2 0F 5D r P4+ MINSD xmm xmm/m64 sse2 Return Minimum Scalar Double-FP Value
0F 5E r P3+ DIVPS xmm xmm/m128 sse1 Divide Packed Single-FP Values
F3 0F 5E r P3+ DIVSS xmm xmm/m32 sse1 Divide Scalar Single-FP Values
66 0F 5E r P4+ DIVPD xmm xmm/m128 sse2 Divide Packed Double-FP Values
F2 0F 5E r P4+ DIVSD xmm xmm/m64 sse2 Divide Scalar Double-FP Values
0F 5F r P3+ MAXPS xmm xmm/m128 sse1 Return Maximum Packed Single-FP Values
F3 0F 5F r P3+ MAXSS xmm xmm/m32 sse1 Return Maximum Scalar Single-FP Value
66 0F 5F r P4+ MAXPD xmm xmm/m128 sse2 Return Maximum Packed Double-FP Values
F2 0F 5F r P4+ MAXSD xmm xmm/m64 sse2 Return Maximum Scalar Double-FP Value
0F 60 r PX+ PUNPCKLBW mm mm/m64 mmx Unpack Low Data
0F 61 r PX+ PUNPCKLWD mm mm/m64 mmx Unpack Low Data
0F 62 r PX+ PUNPCKLDQ mm mm/m64 mmx Unpack Low Data
0F 63 r PX+ PACKSSWB mm mm/m64 mmx Pack with Signed Saturation
0F 64 r PX+ PCMPGTB mm mm/m64 mmx Compare Packed Signed Integers for Greater Than
0F 65 r PX+ PCMPGTW mm mm/m64 mmx Compare Packed Signed Integers for Greater Than
0F 66 r PX+ PCMPGTD mm mm/m64 mmx Compare Packed Signed Integers for Greater Than
0F 67 r PX+ PACKUSWB mm mm/m64 mmx Pack with Unsigned Saturation
0F 68 r PX+ PUNPCKHBW mm mm/m64 mmx Unpack High Data
0F 69 r PX+ PUNPCKHWD mm mm/m64 mmx Unpack High Data
0F 6A r PX+ PUNPCKHDQ mm mm/m64 mmx Unpack High Data
0F 6B r PX+ PACKSSDW mm mm/m64 mmx Pack with Signed Saturation
66 0F 6C r P4+ PUNPCKLQDQ xmm xmm/m128 sse2 Unpack Low Data
66 0F 6D r P4+ PUNPCKHQDQ xmm xmm/m128 sse2 Unpack High Data
0F 6E r PX+ MOVD mm r/m32 mmx Move Doubleword
0F 6F r PX+ MOVQ mm mm/m64 mmx Move Quadword
66 0F 6F r P4+ MOVDQA xmm xmm/m128 sse2 Move Aligned Double Quadword
F3 0F 6F r P4+ MOVDQU xmm xmm/m128 sse2 Move Unaligned Double Quadword
0F 70 r P3+ PSHUFW mm mm/m64 imm8 sse1 Shuffle Packed Words
F2 0F 70 r P4+ PSHUFLW xmm xmm/m128 imm8 sse2 Shuffle Packed Low Words
F3 0F 70 r P4+ PSHUFHW xmm xmm/m128 imm8 sse2 Shuffle Packed High Words
66 0F 70 r P4+ PSHUFD xmm xmm/m128 imm8 sse2 Shuffle Packed Doublewords
0F 71 2 PX+ PSRLW mm imm8 mmx Shift Packed Data Right Logical
66 0F 71 2 P4+ PSRLW xmm imm8 sse2 Shift Packed Data Right Logical
0F 71 4 PX+ PSRAW mm imm8 mmx Shift Packed Data Right Arithmetic
66 0F 71 4 P4+ PSRAW xmm imm8 sse2 Shift Packed Data Right Arithmetic
0F 71 6 PX+ PSLLW mm imm8 mmx Shift Packed Data Left Logical
66 0F 71 6 P4+ PSLLW xmm imm8 sse2 Shift Packed Data Left Logical
0F 72 2 PX+ PSRLD mm imm8 mmx Shift Double Quadword Right Logical
66 0F 72 2 P4+ PSRLD xmm imm8 sse2 Shift Double Quadword Right Logical
0F 72 4 PX+ PSRAD mm imm8 mmx Shift Packed Data Right Arithmetic
66 0F 72 4 P4+ PSRAD xmm imm8 sse2 Shift Packed Data Right Arithmetic
0F 72 6 PX+ PSLLD mm imm8 mmx Shift Packed Data Left Logical
66 0F 72 6 P4+ PSLLD xmm imm8 sse2 Shift Packed Data Left Logical
0F 73 2 PX+ PSRLQ mm imm8 mmx Shift Packed Data Right Logical
66 0F 73 2 P4+ PSRLQ xmm imm8 sse2 Shift Packed Data Right Logical
66 0F 73 3 P4+ PSRLDQ xmm imm8 sse2 Shift Double Quadword Right Logical
0F 73 6 PX+ PSLLQ mm imm8 mmx Shift Packed Data Left Logical
66 0F 73 6 P4+ PSLLQ xmm imm8 sse2 Shift Packed Data Left Logical
66 0F 73 7 P4+ PSLLDQ xmm imm8 sse2 Shift Double Quadword Left Logical
0F 74 r PX+ PCMPEQB mm mm/m64 mmx Compare Packed Data for Equal
66 0F 74 r P4+ PCMPEQB xmm xmm/m128 sse2 Compare Packed Data for Equal
0F 75 r PX+ PCMPEQW mm mm/m64 mmx Compare Packed Data for Equal
66 0F 75 r P4+ PCMPEQW xmm xmm/m128 sse2 Compare Packed Data for Equal
0F 76 r PX+ PCMPEQD mm mm/m64 mmx Compare Packed Data for Equal
66 0F 76 r P4+ PCMPEQD xmm xmm/m128 sse2 Compare Packed Data for Equal
0F 77 PX+ EMMS mmx Empty MMX Technology State
66 0F 7C r P4++ HADDPD xmm xmm/m128 sse3 Packed Double-FP Horizontal Add
F2 0F 7C r P4++ HADDPS xmm xmm/m128 sse3 Packed Single-FP Horizontal Add
66 0F 7D r P4++ HSUBPD xmm xmm/m128 sse3 Packed Double-FP Horizontal Subtract
F2 0F 7D r P4++ HSUBPS xmm xmm/m128 sse3 Packed Single-FP Horizontal Subtract
0F 7E r PX+ MOVD r/m32 mm mmx Move Doubleword
0F 7F r PX+ MOVQ mm/m64 mm mmx Move Quadword
66 0F 7F r P4+ MOVDQA xmm/m128 xmm sse2 Move Aligned Double Quadword
F3 0F 7F r P4+ MOVDQU xmm/m128 xmm sse2 Move Unaligned Double Quadword
0F 80 03+ JO rel16/32 o....... Jump short if overflow (OF=1)
0F 81 03+ JNO rel16/32 o....... Jump short if not overflow (OF=0)
0F 82 03+ JB rel16/32 .......c Jump short if below/not above or equal/carry (CF=1)
JNAE rel16/32
JC rel16/32
0F 83 03+ JNB rel16/32 .......c Jump short if not below/above or equal/not carry (CF=0)
JAE rel16/32
JNC rel16/32
0F 84 03+ JZ rel16/32 ....z... Jump short if zero/equal (ZF=0)
JE rel16/32
0F 85 03+ JNZ rel16/32 ....z... Jump short if not zero/not equal (ZF=1)
JNE rel16/32
0F 86 03+ JBE rel16/32 ....z..c Jump short if below or equal/not above (CF=1 AND ZF=1)
JNA rel16/32
0F 87 03+ JNBE rel16/32 ....z..c Jump short if not below or equal/above (CF=0 AND ZF=0)
JA rel16/32
0F 88 03+ JS rel16/32 ...s.... Jump short if sign (SF=1)
0F 89 03+ JNS rel16/32 ...s.... Jump short if not sign (SF=0)
0F 8A 03+ JP rel16/32 ......p. Jump short if parity/parity even (PF=1)
JPE rel16/32
0F 8B 03+ JNP rel16/32 ......p. Jump short if not parity/parity odd
JPO rel16/32
0F 8C 03+ JL rel16/32 o..s.... Jump short if less/not greater (SF!=OF)
JNGE rel16/32
0F 8D 03+ JNL rel16/32 o..s.... Jump short if not less/greater or equal (SF=OF)
JGE rel16/32
0F 8E 03+ JLE rel16/32 o..sz... Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel16/32
0F 8F 03+ JNLE rel16/32 o..sz... Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel16/32
0F 90 0 03+ D12 SETO r/m8 o....... Set Byte on Condition - overflow (OF=1)
0F 91 0 03+ D12 SETNO r/m8 o....... Set Byte on Condition - not overflow (OF=0)
0F 92 0 03+ D12 SETB r/m8 .......c Set Byte on Condition - below/not above or equal/carry (CF=1)
SETNAE r/m8
SETC r/m8
0F 93 0 03+ D12 SETNB r/m8 .......c Set Byte on Condition - not below/above or equal/not carry (CF=0)
SETAE r/m8
SETNC r/m8
0F 94 0 03+ D12 SETZ r/m8 ....z... Set Byte on Condition - zero/equal (ZF=0)
SETE r/m8
0F 95 0 03+ D12 SETNZ r/m8 ....z... Set Byte on Condition - not zero/not equal (ZF=1)
SETNE r/m8
0F 96 0 03+ D12 SETBE r/m8 ....z..c Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
SETNA r/m8
0F 97 0 03+ D12 SETNBE r/m8 ....z..c Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETA r/m8
0F 98 0 03+ D12 SETS r/m8 ...s.... Set Byte on Condition - sign (SF=1)
0F 99 0 03+ D12 SETNS r/m8 ...s.... Set Byte on Condition - not sign (SF=0)
0F 9A 0 03+ D12 SETP r/m8 ......p. Set Byte on Condition - parity/parity even (PF=1)
SETPE r/m8
0F 9B 0 03+ D12 SETNP r/m8 ......p. Set Byte on Condition - not parity/parity odd
SETPO r/m8
0F 9C 0 03+ D12 SETL r/m8 o..s.... Set Byte on Condition - less/not greater (SF!=OF)
SETNGE r/m8
0F 9D 0 03+ D12 SETNL r/m8 o..s.... Set Byte on Condition - not less/greater or equal (SF=OF)
SETGE r/m8
0F 9E 0 03+ D12 SETLE r/m8 o..sz... Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNG r/m8
0F 9F 0 03+ D12 SETNLE r/m8 o..sz... Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETG r/m8
0F A0 03+ PUSH FS Push Word, Doubleword or Quadword Onto the Stack
0F A1 03+ POP FS Pop a Value from the Stack
0F A2 04++ CPUID IA32_BIO... EAX ECX ... CPU Identification
0F A3 03+ BT r/m16/32 r16/32 o..szapc .......c o..szap. Bit Test
0F A4 03+ SHLD r/m16/32 r16/32 imm8 o..szapc o..sz.pc o....a.c Double Precision Shift Left
0F A5 03+ SHLD r/m16/32 r16/32 CL o..szapc o..sz.pc o....a.c Double Precision Shift Left
0F A8 03+ PUSH GS Push Word, Doubleword or Quadword Onto the Stack
0F A9 03+ POP GS Pop a Value from the Stack
0F AA 03++ S RSM Flags odiszapc odiszapc Resume from System Management Mode
0F AB 03+ L BTS r/m16/32 r16/32 o..szapc .......c o..szap. Bit Test and Set
0F AC 03+ SHRD r/m16/32 r16/32 imm8 o..szapc o..sz.pc o....a.c Double Precision Shift Right
0F AD 03+ SHRD r/m16/32 r16/32 CL o..szapc o..sz.pc o....a.c Double Precision Shift Right
0F AE 0 P2++ FXSAVE m512 ST ST1 ... Save x87 FPU, MMX, XMM, and MXCSR State
0F AE 1 P2++ FXRSTOR ST ST1 ST2 ... Restore x87 FPU, MMX, XMM, and MXCSR State
0F AE 2 P3+ LDMXCSR m32 sse1 Load MXCSR Register
0F AE 3 P3+ STMXCSR m32 sse1 Store MXCSR Register State
0F AE 5 P4+ LFENCE sse2 Load Fence
0F AE 6 P4+ MFENCE sse2 Memory Fence
0F AE 7 P3+ SFENCE sse1 Store Fence
0F AE 7 P4+ CLFLUSH m8 sse2 Flush Cache Line
0F AF r 03+ IMUL r16/32 r/m16/32 o..szapc o......c ...szap. Signed Multiply
0F B0 r 04+ L CMPXCHG r/m8 AL r8 o..szapc o..szapc Compare and Exchange
0F B1 r 04+ L CMPXCHG r/m16/32 eAX r16/32 o..szapc o..szapc Compare and Exchange
0F B2 r 03+ LSS SS r16/32 m16:16/32 Load Far Pointer
0F B3 03+ L BTR r/m16/32 r16/32 o..szapc .......c o..szap. Bit Test and Reset
0F B4 r 03+ LFS FS r16/32 m16:16/32 Load Far Pointer
0F B5 r 03+ LGS GS r16/32 m16:16/32 Load Far Pointer
0F B6 r 03+ MOVZX r16/32 r/m8 Move with Zero-Extend
0F B7 r 03+ MOVZX r16/32 r/m16 Move with Zero-Extend
0F B9 r 02+ M13 UD r r/m Undefined Instruction
0F BA 4 03+ BT r/m16/32 imm8 o..szapc .......c o..szap. Bit Test
0F BA 5 03+ L BTS r/m16/32 imm8 o..szapc .......c o..szap. Bit Test and Set
0F BA 6 03+ L BTR r/m16/32 imm8 o..szapc .......c o..szap. Bit Test and Reset
0F BA 7 03+ L BTC r/m16/32 imm8 o..szapc .......c o..szap. Bit Test and Complement
0F BB 03+ L BTC r/m16/32 r16/32 o..szapc .......c o..szap. Bit Test and Complement
0F BC 03+ BSF r16/32 r/m16/32 o..szapc ....z... o..s.apc Bit Scan Forward
0F BD 03+ BSR r16/32 r/m16/32 o..szapc ....z... o..s.apc Bit Scan Reverse
0F BE r 03+ MOVSX r16/32 r/m8 Move with Sign-Extension
0F BF r 03+ MOVSX r16/32 r/m16 Move with Sign-Extension
0F C0 r 04+ L XADD r/m8 r8 o..szapc o..szapc Exchange and Add
0F C1 r 04+ L XADD r/m16/32 r16/32 o..szapc o..szapc Exchange and Add
0F C2 r P3+ CMPPS xmm xmm/m128 imm8 sse1 Compare Packed Single-FP Values
F3 0F C2 r P3+ CMPSS xmm xmm/m32 imm8 sse1 Compare Scalar Single-FP Values
66 0F C2 r P4+ CMPPD xmm xmm/m128 imm8 sse2 Compare Packed Double-FP Values
F2 0F C2 r P4+ CMPSD xmm xmm/m64 imm8 sse2 Compare Scalar Double-FP Values
0F C3 r P4+ MOVNTI m32 r32 sse2 Store Doubleword Using Non-Temporal Hint
0F C4 r P3+ PINSRW mm r32 imm8 sse1 Insert Word
PINSRW mm m16 imm8
66 0F C4 r P3+ PINSRW xmm r32 imm8 sse1 Insert Word
PINSRW xmm m16 imm8
0F C5 r P3+ PEXTRW r32 mm imm8 sse1 Extract Word
66 0F C5 r P3+ PEXTRW r32 xmm imm8 sse1 Extract Word
0F C6 r P3+ SHUFPS xmm xmm/m128 imm8 sse1 Shuffle Packed Single-FP Values
66 0F C6 r P4+ SHUFPD xmm xmm/m128 imm8 sse2 Shuffle Packed Double-FP Values
0F C7 1 P1+ L CMPXCHG8B m64 EAX EDX ... ....z... ....z... Compare and Exchange Bytes
0F C8+r 04+ BSWAP r16/32 Byte Swap
66 0F D0 r P4++ ADDSUBPD xmm xmm/m128 sse3 Packed Double-FP Add/Subtract
F2 0F D0 r P4++ ADDSUBPS xmm xmm/m128 sse3 Packed Single-FP Add/Subtract
0F D1 r PX+ PSRLW mm mm/m64 mmx Shift Packed Data Right Logical
0F D2 r PX+ PSRLD mm mm/m64 mmx Shift Packed Data Right Logical
0F D3 r PX+ PSRLQ mm mm/m64 mmx Shift Packed Data Right Logical
0F D4 r P4+ PADDQ mm mm/m64 sse2 Add Packed Quadword Integers
66 0F D4 r P4+ PADDQ xmm xmm/m128 sse2 Add Packed Quadword Integers
0F D5 r PX+ PMULLW mm mm/m64 mmx Multiply Packed Signed Integers and Store Low Result
F3 0F D6 r P4+ MOVQ2DQ xmm mm sse2 Move Quadword from MMX Technology to XMM Register
F2 0F D6 r P4+ MOVDQ2Q mm xmm sse2 Move Quadword from XMM to MMX Technology Register
0F D7 r P3+ PMOVMSKB r32 mm sse1 Move Byte Mask
66 0F D7 r P3+ PMOVMSKB r32 xmm sse1 Move Byte Mask
0F D8 r PX+ PSUBUSB mm mm/m64 mmx Subtract Packed Unsigned Integers with Unsigned Saturation
0F D9 r PX+ PSUBUSW mm mm/m64 mmx Subtract Packed Unsigned Integers with Unsigned Saturation
0F DA r P3+ PMINUB mm mm/m64 sse1 Minimum of Packed Unsigned Byte Integers
66 0F DA r P3+ PMINUB xmm xmm/m128 sse1 Minimum of Packed Unsigned Byte Integers
0F DB r PX+ PAND mm mm/m64 mmx Logical AND
0F DC r PX+ PADDUSB mm mm/m64 mmx Add Packed Unsigned Integers with Unsigned Saturation
0F DD r PX+ PADDUSW mm mm/m64 mmx Add Packed Unsigned Integers with Unsigned Saturation
0F DE r P3+ PMAXUB mm mm/m64 sse1 Maximum of Packed Unsigned Byte Integers
66 0F DE r P3+ PMAXUB xmm xmm/m128 sse1 Maximum of Packed Unsigned Byte Integers
0F DF r PX+ PANDN mm mm/m64 mmx Logical AND NOT
0F E0 r P3+ PAVGB mm mm/m64 sse1 Average Packed Integers
66 0F E0 r P3+ PAVGB xmm xmm/m128 sse1 Average Packed Integers
0F E1 r PX+ PSRAW mm mm/m64 mmx Shift Packed Data Right Arithmetic
0F E2 r PX+ PSRAD mm mm/m64 mmx Shift Packed Data Right Arithmetic
0F E3 r P3+ PAVGW mm mm/m64 sse1 Average Packed Integers
66 0F E3 r P3+ PAVGW xmm xmm/m128 sse1 Average Packed Integers
0F E4 r P3+ PMULHUW mm mm/m64 sse1 Multiply Packed Unsigned Integers and Store High Result
66 0F E4 r P3+ PMULHUW xmm xmm/m128 sse1 Multiply Packed Unsigned Integers and Store High Result
0F E5 r PX+ PMULHW mm mm/m64 mmx Multiply Packed Signed Integers and Store High Result
F2 0F E6 r P4+ CVTPD2DQ xmm xmm/m128 sse2 Convert Packed Double-FP Values to Packed DW Integers
66 0F E6 r P4+ CVTTPD2DQ xmm xmm/m128 sse2 Convert with Trunc. Packed Double-FP Values to Packed DW Integers
F3 0F E6 r P4+ CVTDQ2PD xmm xmm/m128 sse2 Convert Packed DW Integers to Packed Double-FP Values
0F E7 r P3+ MOVNTQ m64 mm sse1 Store of Quadword Using Non-Temporal Hint
66 0F E7 r P4+ MOVNTDQ m128 xmm sse2 Store Double Quadword Using Non-Temporal Hint
0F E8 r PX+ PSUBSB mm mm/m64 mmx Subtract Packed Signed Integers with Signed Saturation
0F E9 r PX+ PSUBSW mm mm/m64 mmx Subtract Packed Signed Integers with Signed Saturation
0F EA r P3+ PMINSW mm mm/m64 sse1 Minimum of Packed Signed Word Integers
66 0F EA r P3+ PMINSW xmm xmm/m128 sse1 Minimum of Packed Signed Word Integers
0F EB r PX+ POR mm mm/m64 mmx Bitwise Logical OR
0F EC r PX+ PADDSB mm mm/m64 mmx Add Packed Signed Integers with Signed Saturation
0F ED r PX+ PADDSW mm mm/m64 mmx Add Packed Signed Integers with Signed Saturation
0F EE r P3+ PMAXSW mm mm/m64 sse1 Maximum of Packed Signed Word Integers
66 0F EE r P3+ PMAXSW xmm xmm/m128 sse1 Maximum of Packed Signed Word Integers
0F EF r PX+ PXOR mm mm/m64 mmx Logical Exclusive OR
F2 0F F0 r P4++ LDDQU xmm m128 sse3 Load Unaligned Integer 128 Bits
0F F1 r PX+ PSLLW mm mm/m64 mmx Shift Packed Data Left Logical
0F F2 r PX+ PSLLD mm mm/m64 mmx Shift Packed Data Left Logical
0F F3 r PX+ PSLLQ mm mm/m64 mmx Shift Packed Data Left Logical
0F F4 r P4+ PMULUDQ mm mm/m64 sse2 Multiply Packed Unsigned DW Integers
66 0F F4 r P4+ PMULUDQ xmm xmm/m128 sse2 Multiply Packed Unsigned DW Integers
0F F5 r PX+ PMADDWD mm mm/m64 mmx Multiply and Add Packed Integers
0F F6 r P3+ PSADBW mm mm/m64 sse1 Compute Sum of Absolute Differences
66 0F F6 r P3+ PSADBW xmm xmm/m128 sse1 Compute Sum of Absolute Differences
0F F7 r P3+ MASKMOVQ m64 mm mm sse1 Store Selected Bytes of Quadword
66 0F F7 r P4+ MASKMOVDQU m128 xmm xmm sse2 Store Selected Bytes of Double Quadword
0F F8 r PX+ PSUBB mm mm/m64 mmx Subtract Packed Integers
0F F9 r PX+ PSUBW mm mm/m64 mmx Subtract Packed Integers
0F FA r PX+ PSUBD mm mm/m64 mmx Subtract Packed Integers
0F FB r P4+ PSUBQ mm mm/m64 sse2 Subtract Packed Quadword Integers
66 0F FB r P4+ PSUBQ xmm xmm/m128 sse2 Subtract Packed Quadword Integers
0F FC r PX+ PADDB mm mm/m64 mmx Add Packed Integers
0F FD r PX+ PADDW mm mm/m64 mmx Add Packed Integers
0F FE r PX+ PADDD mm mm/m64 mmx Add Packed Integers

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General notes:

  1. SAL
    1. sandpile.org -- IA-32 architecture -- opcode groups
  2. D6 and F1 opcodes
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 3: System Programming Guide, Interrupt and Exception Handling
  3. SALC
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
  4. FNENI and FNDISI
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
  5. FNSETPM
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
  6. FFREEP
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  7. X87 aliases
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  8. INT1, ICEBP
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
  9. TEST
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
  10. 0F0D NOP
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
  11. MOV from/to CRn, DRn, TRn
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
  12. SETcc
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
  13. 0FB9 UD
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

Create a hypertext reference to this edition's opcode (append hexadecimal opcode at the end of the following line):

http://ref.x86asm.net/coder32.html#x

Your Notes: