X86 Opcode and Instruction Reference Home

Other editions: coder32-abc, coder-abc, geek32-abc, geek64-abc, geek-abc
32/64-bit ModR/M Byte | 32/64-bit SIB Byte
16-bit ModR/M Byte

alphabetic index:

 A    B    C    D    E    F    G    H    I    J    L    M    N    O    P    R    S    T    U    V    W    X  
mnemonic op1 op2 op3 op4 iext pf 0F po so o proc st m rl x tested f modif f def f undef f f values description, notes                                        
ADC r/m8 r8 10 r L .......c o..szapc o..szapc Add with Carry
ADC r/m16/32/64 r16/32/64 11 r L .......c o..szapc o..szapc Add with Carry
ADC r8 r/m8 12 r .......c o..szapc o..szapc Add with Carry
ADC r16/32/64 r/m16/32/64 13 r .......c o..szapc o..szapc Add with Carry
ADC AL imm8 14 .......c o..szapc o..szapc Add with Carry
ADC rAX imm16/32 15 .......c o..szapc o..szapc Add with Carry
ADC r/m8 imm8 80 2 L .......c o..szapc o..szapc Add with Carry
ADC r/m16/32/64 imm16/32 81 2 L .......c o..szapc o..szapc Add with Carry
ADC r/m16/32/64 imm8 83 2 L .......c o..szapc o..szapc Add with Carry
ADD r/m8 r8 00 r L o..szapc o..szapc Add
ADD r/m16/32/64 r16/32/64 01 r L o..szapc o..szapc Add
ADD r8 r/m8 02 r o..szapc o..szapc Add
ADD r16/32/64 r/m16/32/64 03 r o..szapc o..szapc Add
ADD AL imm8 04 o..szapc o..szapc Add
ADD rAX imm16/32 05 o..szapc o..szapc Add
ADD r/m8 imm8 80 0 L o..szapc o..szapc Add
ADD r/m16/32/64 imm16/32 81 0 L o..szapc o..szapc Add
ADD r/m16/32/64 imm8 83 0 L o..szapc o..szapc Add
ADDPD xmm xmm/m128 sse2 66 0F 58 r Add Packed Double-FP Values
ADDPS xmm xmm/m128 sse1 0F 58 r Add Packed Single-FP Values
ADDSD xmm xmm/m64 sse2 F2 0F 58 r Add Scalar Double-FP Values
ADDSS xmm xmm/m32 sse1 F3 0F 58 r Add Scalar Single-FP Values
ADDSUBPD xmm xmm/m128 sse3 66 0F D0 r Packed Double-FP Add/Subtract
ADDSUBPS xmm xmm/m128 sse3 F2 0F D0 r Packed Single-FP Add/Subtract
AND r/m8 r8 20 r L o..szapc o..sz.pc .....a.. o......c Logical AND
AND r/m16/32/64 r16/32/64 21 r L o..szapc o..sz.pc .....a.. o......c Logical AND
AND r8 r/m8 22 r o..szapc o..sz.pc .....a.. o......c Logical AND
AND r16/32/64 r/m16/32/64 23 r o..szapc o..sz.pc .....a.. o......c Logical AND
AND AL imm8 24 o..szapc o..sz.pc .....a.. o......c Logical AND
AND rAX imm16/32 25 o..szapc o..sz.pc .....a.. o......c Logical AND
AND r/m8 imm8 80 4 L o..szapc o..sz.pc .....a.. o......c Logical AND
AND r/m16/32/64 imm16/32 81 4 L o..szapc o..sz.pc .....a.. o......c Logical AND
AND r/m16/32/64 imm8 83 4 L o..szapc o..sz.pc .....a.. o......c Logical AND
ANDNPD xmm xmm/m128 sse2 66 0F 55 r Bitwise Logical AND NOT of Packed Double-FP Values
ANDNPS xmm xmm/m128 sse1 0F 55 r Bitwise Logical AND NOT of Packed Single-FP Values
ANDPD xmm xmm/m128 sse2 66 0F 54 r Bitwise Logical AND of Packed Double-FP Values
ANDPS xmm xmm/m128 sse1 0F 54 r Bitwise Logical AND of Packed Single-FP Values
BLENDPD xmm xmm/m128 imm8 sse41 66 0F 3A 0D r C2++ D33 Blend Packed Double-FP Values
BLENDPS xmm xmm/m128 imm8 sse41 66 0F 3A 0C r C2++ D33 Blend Packed Single-FP Values
BSF r16/32/64 r/m16/32/64 0F BC r D27 o..szapc ....z... o..s.apc Bit Scan Forward
BSR r16/32/64 r/m16/32/64 0F BD r D27 o..szapc ....z... o..s.apc Bit Scan Reverse
BSWAP r16/32/64 0F C8+r D29 Byte Swap
BT r/m16/32/64 r16/32/64 0F A3 r o..szapc .......c o..szap. Bit Test
BT r/m16/32/64 imm8 0F BA 4 o..szapc .......c o..szap. Bit Test
BTC r/m16/32/64 imm8 0F BA 7 L o..szapc .......c o..szap. Bit Test and Complement
BTC r/m16/32/64 r16/32/64 0F BB r L o..szapc .......c o..szap. Bit Test and Complement
BTR r/m16/32/64 r16/32/64 0F B3 r L o..szapc .......c o..szap. Bit Test and Reset
BTR r/m16/32/64 imm8 0F BA 6 L o..szapc .......c o..szap. Bit Test and Reset
BTS r/m16/32/64 r16/32/64 0F AB r L o..szapc .......c o..szap. Bit Test and Set
BTS r/m16/32/64 imm8 0F BA 5 L o..szapc .......c o..szap. Bit Test and Set
CALL rel16/32 E8 D31 Call Procedure
CALL r/m16/32 FF 2 Call Procedure
CALL r/m64 FF 2 D31 E Call Procedure
CALLF m16:16/32/64 FF 3 D12 Call Procedure
CBW AX AL 98 E Convert
CWDE EAX AX
CDQE RAX EAX
CLC F8 .......c .......c .......c Clear Carry Flag
CLD FC .d...... .d...... .d...... Clear Direction Flag
CLFLUSH m8 sse2 0F AE 7 Flush Cache Line
CLI FA f1 ..i..... ..i..... ..i..... Clear Interrupt Flag
CLTS CR0 0F 06 0 Clear Task-Switched Flag in CR0
CMC F5 .......c .......c .......c Complement Carry Flag
CMOVB r16/32/64 r/m16/32/64 0F 42 r D22 .......c Conditional Move - below/not above or equal/carry (CF=1)
CMOVNAE r16/32/64 r/m16/32/64
CMOVC r16/32/64 r/m16/32/64
CMOVBE r16/32/64 r/m16/32/64 0F 46 r D22 ....z..c Conditional Move - below or equal/not above (CF=1 OR ZF=1)
CMOVNA r16/32/64 r/m16/32/64
CMOVL r16/32/64 r/m16/32/64 0F 4C r D22 o..s.... Conditional Move - less/not greater (SF!=OF)
CMOVNGE r16/32/64 r/m16/32/64
CMOVLE r16/32/64 r/m16/32/64 0F 4E r D22 o..sz... Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNG r16/32/64 r/m16/32/64
CMOVNB r16/32/64 r/m16/32/64 0F 43 r D22 .......c Conditional Move - not below/above or equal/not carry (CF=0)
CMOVAE r16/32/64 r/m16/32/64
CMOVNC r16/32/64 r/m16/32/64
CMOVNBE r16/32/64 r/m16/32/64 0F 47 r D22 ....z..c Conditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVA r16/32/64 r/m16/32/64
CMOVNL r16/32/64 r/m16/32/64 0F 4D r D22 o..s.... Conditional Move - not less/greater or equal (SF=OF)
CMOVGE r16/32/64 r/m16/32/64
CMOVNLE r16/32/64 r/m16/32/64 0F 4F r D22 o..sz... Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVG r16/32/64 r/m16/32/64
CMOVNO r16/32/64 r/m16/32/64 0F 41 r D22 o....... Conditional Move - not overflow (OF=0)
CMOVNP r16/32/64 r/m16/32/64 0F 4B r D22 ......p. Conditional Move - not parity/parity odd (PF=0)
CMOVPO r16/32/64 r/m16/32/64
CMOVNS r16/32/64 r/m16/32/64 0F 49 r D22 ...s.... Conditional Move - not sign (SF=0)
CMOVNZ r16/32/64 r/m16/32/64 0F 45 r D22 ....z... Conditional Move - not zero/not equal (ZF=0)
CMOVNE r16/32/64 r/m16/32/64
CMOVO r16/32/64 r/m16/32/64 0F 40 r D22 o....... Conditional Move - overflow (OF=1)
CMOVP r16/32/64 r/m16/32/64 0F 4A r D22 ......p. Conditional Move - parity/parity even (PF=1)
CMOVPE r16/32/64 r/m16/32/64
CMOVS r16/32/64 r/m16/32/64 0F 48 r D22 ...s.... Conditional Move - sign (SF=1)
CMOVZ r16/32/64 r/m16/32/64 0F 44 r D22 ....z... Conditional Move - zero/equal (ZF=1)
CMOVE r16/32/64 r/m16/32/64
CMP r/m8 r8 38 r o..szapc o..szapc Compare Two Operands
CMP r/m16/32/64 r16/32/64 39 r o..szapc o..szapc Compare Two Operands
CMP r8 r/m8 3A r o..szapc o..szapc Compare Two Operands
CMP r16/32/64 r/m16/32/64 3B r o..szapc o..szapc Compare Two Operands
CMP AL imm8 3C o..szapc o..szapc Compare Two Operands
CMP rAX imm16/32 3D o..szapc o..szapc Compare Two Operands
CMP r/m8 imm8 80 7 o..szapc o..szapc Compare Two Operands
CMP r/m16/32/64 imm16/32 81 7 o..szapc o..szapc Compare Two Operands
CMP r/m16/32/64 imm8 83 7 o..szapc o..szapc Compare Two Operands
CMPPD xmm xmm/m128 imm8 sse2 66 0F C2 r Compare Packed Double-FP Values
CMPPS xmm xmm/m128 imm8 sse1 0F C2 r Compare Packed Single-FP Values
CMPS m8 m8 A6 .d...... o..szapc o..szapc Compare String Operands
CMPSB m8 m8
CMPS m16/32/64 m16/32/64 A7 E .d...... o..szapc o..szapc Compare String Operands
CMPSW m16 m16
CMPSD m32 m32
CMPSQ m64 m64
CMPSD xmm xmm/m64 imm8 sse2 F2 0F C2 r Compare Scalar Double-FP Values
CMPSS xmm xmm/m32 imm8 sse1 F3 0F C2 r Compare Scalar Single-FP Values
CMPXCHG r/m8 AL r8 0F B0 r D24 L o..szapc o..szapc Compare and Exchange
CMPXCHG r/m16/32/64 rAX r16/32/64 0F B1 r D24 L o..szapc o..szapc Compare and Exchange
CMPXCHG8B m64 EAX EDX ... 0F C7 1 D28 L ....z... ....z... Compare and Exchange Bytes
CMPXCHG8B m64 EAX EDX ... 0F C7 1 D28 E L ....z... ....z... Compare and Exchange Bytes
CMPXCHG16B m128 RAX RDX ...
COMISD xmm xmm/m64 sse2 66 0F 2F r ....z.pc ....z.pc Compare Scalar Ordered Double-FP Values and Set EFLAGS
COMISS xmm xmm/m32 sse1 0F 2F r ....z.pc ....z.pc Compare Scalar Ordered Single-FP Values and Set EFLAGS
CPUID IA32_BIOS_SIG… EAX ECX ... 0F A2 CPU Identification
CRC32 r32/64 r/m8 sse42 F2 0F 38 F0 r C2++ D33 Accumulate CRC32 Value
CRC32 r32/64 r/m16/32/64 sse42 F2 0F 38 F1 r C2++ D33 Accumulate CRC32 Value
CVTDQ2PD xmm xmm/m128 sse2 F3 0F E6 r Convert Packed DW Integers to Double-FP Values
CVTDQ2PS xmm xmm/m128 sse2 0F 5B r Convert Packed DW Integers to Single-FP Values
CVTPD2DQ xmm xmm/m128 sse2 F2 0F E6 r Convert Packed Double-FP Values to DW Integers
CVTPD2PI mm xmm/m128 sse2 66 0F 2D r Convert Packed Double-FP Values to DW Integers
CVTPD2PS xmm xmm/m128 sse2 66 0F 5A r Convert Packed Double-FP Values to Single-FP Values
CVTPI2PD xmm mm/m64 sse2 66 0F 2A r Convert Packed DW Integers to Double-FP Values
CVTPI2PS xmm mm/m64 sse1 0F 2A r Convert Packed DW Integers to Single-FP Values
CVTPS2DQ xmm xmm/m128 sse2 66 0F 5B r Convert Packed Single-FP Values to DW Integers
CVTPS2PD xmm xmm/m128 sse2 0F 5A r Convert Packed Single-FP Values to Double-FP Values
CVTPS2PI mm xmm/m64 sse1 0F 2D r Convert Packed Single-FP Values to DW Integers
CVTSD2SI r32/64 xmm/m64 sse2 F2 0F 2D r Convert Scalar Double-FP Value to DW Integer
CVTSD2SS xmm xmm/m64 sse2 F2 0F 5A r Convert Scalar Double-FP Value to Scalar Single-FP Value
CVTSI2SD xmm r/m32/64 sse2 F2 0F 2A r Convert DW Integer to Scalar Double-FP Value
CVTSI2SS xmm r/m32/64 sse1 F3 0F 2A r Convert DW Integer to Scalar Single-FP Value
CVTSS2SD xmm xmm/m32 sse2 F3 0F 5A r Convert Scalar Single-FP Value to Scalar Double-FP Value
CVTSS2SI r32/64 xmm/m32 sse1 F3 0F 2D r Convert Scalar Single-FP Value to DW Integer
CVTTPD2DQ xmm xmm/m128 sse2 66 0F E6 r Convert with Trunc. Packed Double-FP Values to DW Integers
CVTTPD2PI mm xmm/m128 sse2 66 0F 2C r Convert with Trunc. Packed Double-FP Values to DW Integers
CVTTPS2DQ xmm xmm/m128 sse2 F3 0F 5B r Convert with Trunc. Packed Single-FP Values to DW Integers
CVTTPS2PI mm xmm/m64 sse1 0F 2C r Convert with Trunc. Packed Single-FP Values to DW Integers
CVTTSD2SI r32/64 xmm/m64 sse2 F2 0F 2C r Conv. with Trunc. Scalar Double-FP Value to Signed DW Int
CVTTSS2SI r32/64 xmm/m32 sse1 F3 0F 2C r Convert with Trunc. Scalar Single-FP Value to DW Integer
CWD DX AX 99 E Convert
CDQ EDX EAX
CQO RDX RAX
DEC r/m8 FE 1 L o..szap. o..szap. Decrement by 1
DEC r/m16/32/64 FF 1 L o..szap. o..szap. Decrement by 1
DIV AL AH AX r/m8 F6 6 o..szapc o..szapc Unsigned Divide
DIV rDX rAX r/m16/32/64 F7 6 o..szapc o..szapc Unsigned Divide
DIVPD xmm xmm/m128 sse2 66 0F 5E r Divide Packed Double-FP Values
DIVPS xmm xmm/m128 sse1 0F 5E r Divide Packed Single-FP Values
DIVSD xmm xmm/m64 sse2 F2 0F 5E r Divide Scalar Double-FP Values
DIVSS xmm xmm/m32 sse1 F3 0F 5E r Divide Scalar Single-FP Values
DPPD xmm xmm/m128 sse41 66 0F 3A 41 r C2++ D33 Dot Product of Packed Double-FP Values
DPPS xmm xmm/m128 sse41 66 0F 3A 40 r C2++ D33 Dot Product of Packed Single-FP Values
EMMS mmx 0F 77 Empty MMX Technology State
ENTER rBP imm16 imm8 C8 E Make Stack Frame for Procedure Parameters
EXTRACTPS r/m32 xmm imm8 sse41 66 0F 3A 17 r C2++ D33 Extract Packed Single-FP Value
F2XM1 ST D9 F0 6 0123 .1.. 0.23 Compute 2x-1
FABS ST D9 E1 4 0123 .1.. 0.23 Absolute Value
FADD ST m32real D8 0 0123 .1.. 0.23 Add
FADD ST STi
FADD ST m64real DC 0 0123 .1.. 0.23 Add
FADD STi ST DC 0 0123 .1.. 0.23 Add
FADDP STi ST DE 0 p 0123 .1.. 0.23 Add and Pop
FADDP ST1 ST DE C1 0 p 0123 .1.. 0.23 Add and Pop
FBLD ST m80dec DF 4 s 0123 .1.. 0.23 Load Binary Coded Decimal
FBSTP m80dec ST DF 6 p 0123 .1.. 0.23 Store BCD Integer and Pop
FCHS ST D9 E0 4 0123 .1.. 0.23 Change Sign
FCLEX 9B DB E2 4 0123 0123 Clear Exceptions
FCMOVB ST STi DA 0 .......c 0123 .1.. 0.23 FP Conditional Move - below (CF=1)
FCMOVBE ST STi DA 2 ....z... 0123 .1.. 0.23 FP Conditional Move - below or equal (CF=1 or ZF=1)
FCMOVE ST STi DA 1 ....z... 0123 .1.. 0.23 FP Conditional Move - equal (ZF=1)
FCMOVNB ST STi DB 0 .......c 0123 .1.. 0.23 FP Conditional Move - not below (CF=0)
FCMOVNBE ST STi DB 2 ....z... 0123 .1.. 0.23 FP Conditional Move - below or equal (CF=0 and ZF=0)
FCMOVNE ST STi DB 1 ....z... 0123 .1.. 0.23 FP Conditional Move - not equal (ZF=0)
FCMOVNU ST STi DB 3 ......p. 0123 .1.. 0.23 FP Conditional Move - not unordered (PF=0)
FCMOVU ST STi DA 3 ......p. 0123 .1.. 0.23 FP Conditional Move - unordered (PF=1)
FCOM ST STi/m32real D8 2 0123 0123 Compare Real
FCOM ST ST1 D8 D1 2 0123 0123 Compare Real
FCOM ST m64real DC 2 0123 0123 Compare Real
FCOM2 ST STi DC 2 U8 0123 0123 Compare Real
FCOMI ST STi DB 6 o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS
FCOMIP ST STi DF 6 p o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS and Pop
FCOMP ST STi/m32real D8 3 p 0123 0123 Compare Real and Pop
FCOMP ST ST1 D8 D9 3 p 0123 0123 Compare Real and Pop
FCOMP ST m64real DC 3 p 0123 0123 Compare Real and Pop
FCOMP3 ST STi DC 3 U8 p 0123 0123 Compare Real and Pop
FCOMP5 ST STi DE 2 U8 p 0123 0123 Compare Real and Pop
FCOMPP ST ST1 DE D9 3 P 0123 0123 Compare Real and Pop Twice
FCOS ST D9 FF 7 0123 .12. 0..3 Cosine
FDECSTP D9 F6 6 0123 .1.. 0.23 .0.. Decrement Stack-Top Pointer
FDIV ST m32real D8 6 0123 .1.. 0.23 Divide
FDIV ST STi
FDIV ST m64real DC 6 0123 .1.. 0.23 Divide
FDIV STi ST DC 7 0123 .1.. 0.23 Divide and Pop
FDIVP STi ST DE 7 p 0123 .1.. 0.23 Divide and Pop
FDIVP ST1 ST DE F9 7 p 0123 .1.. 0.23 Divide and Pop
FDIVR ST m32real D8 7 0123 .1.. 0.23 Reverse Divide
FDIVR ST STi
FDIVR STi ST DC 6 0123 .1.. 0.23 Reverse Divide
FDIVR ST m64real DC 7 0123 .1.. 0.23 Reverse Divide
FDIVRP STi ST DE 6 p 0123 .1.. 0.23 Reverse Divide and Pop
FDIVRP ST1 ST DE F1 6 p 0123 .1.. 0.23 Reverse Divide and Pop
FFREE STi DD 0 0123 0123 Free Floating-Point Register
FFREEP STi DF 0 D7 p 0123 0123 Free Floating-Point Register and Pop
FIADD ST m32int DA 0 0123 .1.. 0.23 Add
FIADD ST m16int DE 0 0123 .1.. 0.23 Add
FICOM ST m32int DA 2 0123 0123 Compare Integer
FICOM ST m16int DE 2 0123 0123 Compare Integer
FICOMP ST m32int DA 3 p 0123 0123 Compare Integer and Pop
FICOMP ST m16int DE 3 p 0123 0123 Compare Integer and Pop
FIDIV ST m32int DA 6 0123 .1.. 0.23 Divide
FIDIV ST m16int DE 6 0123 .1.. 0.23 Divide
FIDIVR ST m32int DA 7 0123 .1.. 0.23 Reverse Divide
FIDIVR ST m16int DE 7 0123 .1.. 0.23 Reverse Divide
FILD ST m32int DB 0 s 0123 .1.. 0.23 Load Integer
FILD ST m16int DF 0 s 0123 .1.. 0.23 Load Integer
FILD ST m64int DF 5 s 0123 .1.. 0.23 Load Integer
FIMUL ST m32int DA 1 0123 .1.. 0.23 Multiply
FIMUL ST m16int DE 1 0123 .1.. 0.23 Multiply
FINCSTP D9 F7 6 0123 .1.. 0.23 .0.. Increment Stack-Top Pointer
FINIT 9B DB E3 4 0123 0000 Initialize Floating-Point Unit
FIST m32int ST DB 2 0123 .1.. 0.23 Store Integer
FIST m16int ST DF 2 0123 .1.. 0.23 Store Integer
FISTP m32int ST DB 3 p 0123 .1.. 0.23 Store Integer and Pop
FISTP m16int ST DF 3 p 0123 .1.. 0.23 Store Integer and Pop
FISTP m64int ST DF 7 p 0123 .1.. 0.23 Store Integer and Pop
FISTTP m32int ST sse3 DB 1 p 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISTTP m64int ST sse3 DD 1 p 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISTTP m16int ST sse3 DF 1 p 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISUB ST m32int DA 4 0123 .1.. 0.23 Subtract
FISUB ST m16int DE 4 0123 .1.. 0.23 Subtract
FISUBR ST m32int DA 5 0123 .1.. 0.23 Reverse Subtract
FISUBR ST m16int DE 5 0123 .1.. 0.23 Reverse Subtract
FLD ST STi/m32real D9 0 s 0123 .1.. 0.23 Load Floating Point Value
FLD ST m80real DB 5 s 0123 .1.. 0.23 Load Floating Point Value
FLD ST m64real DD 0 s 0123 .1.. 0.23 Load Floating Point Value
FLD1 ST D9 E8 5 s 0123 .1.. 0.23 Load Constant +1.0
FLDCW m16 D9 5 0123 0123 Load x87 FPU Control Word
FLDENV m14/28 D9 4 0123 0123 Load x87 FPU Environment
FLDL2E ST D9 EA 5 s 0123 .1.. 0.23 Load Constant log2e
FLDL2T ST D9 E9 5 s 0123 .1.. 0.23 Load Constant log210
FLDLG2 ST D9 EC 5 s 0123 .1.. 0.23 Load Constant log102
FLDLN2 ST D9 ED 5 s 0123 .1.. 0.23 Load Constant loge2
FLDPI ST D9 EB 5 s 0123 .1.. 0.23 Load Constant π
FLDZ ST D9 EE 5 s 0123 .1.. 0.23 Load Constant +0.0
FMUL ST m32real D8 1 0123 .1.. 0.23 Multiply
FMUL ST STi
FMUL ST m64real DC 1 0123 .1.. 0.23 Multiply
FMUL STi ST DC 1 0123 .1.. 0.23 Multiply
FMULP STi ST DE 1 p 0123 .1.. 0.23 Multiply and Pop
FMULP ST1 ST DE C9 1 p 0123 .1.. 0.23 Multiply and Pop
FNCLEX DB E2 4 0123 0123 Clear Exceptions
FNDISI nop DB E1 4 D5 Treated as Integer NOP
FNENI nop DB E0 4 D5 Treated as Integer NOP
FNINIT DB E3 4 0123 0000 Initialize Floating-Point Unit
FNOP D9 D0 2 0123 0123 No Operation
FNSAVE m94/108 ST ST1 ... DD 6 0123 0123 0000 Store x87 FPU State
FNSETPM nop DB E4 4 D6 Treated as Integer NOP
FNSTCW m16 D9 7 0123 0123 Store x87 FPU Control Word
FNSTENV m14/28 D9 6 0123 0123 Store x87 FPU Environment
FNSTSW m16 DD 7 0123 0123 Store x87 FPU Status Word
FNSTSW AX DF E0 4 0123 0123 Store x87 FPU Status Word
FPATAN ST1 ST D9 F3 6 p 0123 .1.. 0.23 Partial Arctangent and Pop
FPREM ST ST1 D9 F8 7 0123 0123 Partial Remainder (for compatibility with i8087 and i287)
FPREM1 ST ST1 D9 F5 6 0123 0123 IEEE Partial Remainder
FPTAN ST D9 F2 6 s 0123 .12. 0..3 Partial Tangent
FRNDINT ST D9 FC 7 0123 .1.. 0.23 Round to Integer
FRSTOR ST ST1 ST2 ... DD 4 0123 0123 Restore x87 FPU State
FS FS 64 FS segment override prefix
FSAVE m94/108 ST ST1 ... 9B DD 6 0123 0123 0000 Store x87 FPU State
FSCALE ST ST1 D9 FD 7 0123 .1.. 0.23 Scale
FSIN ST D9 FE 7 0123 .12. 0..3 Sine
FSINCOS ST D9 FB 7 s 0123 .12. 0..3 Sine and Cosine
FSQRT ST D9 FA 7 0123 .1.. 0.23 Square Root
FST m32real ST D9 2 0123 .1.. 0.23 Store Floating Point Value
FST m64real ST DD 2 0123 .1.. 0.23 Store Floating Point Value
FST ST STi DD 2 0123 .1.. 0.23 Store Floating Point Value
FSTCW m16 9B D9 7 0123 0123 Store x87 FPU Control Word
FSTENV m14/28 9B D9 6 0123 0123 Store x87 FPU Environment
FSTP m32real ST D9 3 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP m80real ST DB 7 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP m64real ST DD 3 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP ST STi DD 3 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP1 STi ST D9 3 U8 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP8 STi ST DF 2 U8 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP9 STi ST DF 3 U8 p 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTSW m16 9B DD 7 0123 0123 Store x87 FPU Status Word
FSTSW AX 9B DF E0 4 0123 0123 Store x87 FPU Status Word
FSUB ST m32real D8 4 0123 .1.. 0.23 Subtract
FSUB ST STi
FSUB ST m64real DC 4 0123 .1.. 0.23 Subtract
FSUB STi ST DC 5 0123 .1.. 0.23 Subtract
FSUBP STi ST DE 5 p 0123 .1.. 0.23 Subtract and Pop
FSUBP ST1 ST DE E9 5 p 0123 .1.. 0.23 Subtract and Pop
FSUBR ST m32real D8 5 0123 .1.. 0.23 Reverse Subtract
FSUBR ST STi
FSUBR STi ST DC 4 0123 .1.. 0.23 Reverse Subtract
FSUBR ST m64real DC 5 0123 .1.. 0.23 Reverse Subtract
FSUBRP STi ST DE 4 p 0123 .1.. 0.23 Reverse Subtract and Pop
FSUBRP ST1 ST DE E1 4 p 0123 .1.. 0.23 Reverse Subtract and Pop
FTST ST D9 E4 4 0123 0123 Test
FUCOM ST STi DD 4 0123 0123 Unordered Compare Floating Point Values
FUCOM ST ST1 DD E1 4 0123 0123 Unordered Compare Floating Point Values
FUCOMI ST STi DB 5 o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS
FUCOMIP ST STi DF 5 p o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS and Pop
FUCOMP ST STi DD 5 p 0123 0123 Unordered Compare Floating Point Values and Pop
FUCOMP ST ST1 DD E9 5 p 0123 0123 Unordered Compare Floating Point Values and Pop
FUCOMPP ST ST1 DA E9 5 P 0123 0123 Unordered Compare Floating Point Values and Pop Twice
FWAIT 9B 0123 0123 Check pending unmasked floating-point exceptions
WAIT
FXAM ST D9 E5 4 0123 0123 Examine
FXCH ST STi D9 1 0123 .1.. 0.23 Exchange Register Contents
FXCH ST ST1 D9 C9 1 0123 .1.. 0.23 Exchange Register Contents
FXCH4 ST STi DD 1 U8 0123 .1.. 0.23 Exchange Register Contents
FXCH7 ST STi DF 1 U8 0123 .1.. 0.23 Exchange Register Contents
FXRSTOR ST ST1 ST2 ... 0F AE 1 Restore x87 FPU, MMX, XMM, and MXCSR State
FXRSTOR ST ST1 ST2 ... 0F AE 1 E Restore x87 FPU, MMX, XMM, and MXCSR State
FXSAVE m512 ST ST1 ... 0F AE 0 Save x87 FPU, MMX, XMM, and MXCSR State
FXSAVE m512 ST ST1 ... 0F AE 0 E Save x87 FPU, MMX, XMM, and MXCSR State
FXTRACT ST D9 F4 6 s 0123 .1.. 0.23 Extract Exponent and Significand
FYL2X ST1 ST D9 F1 6 p 0123 .1.. 0.23 Compute y × log2x and Pop
FYL2XP1 ST1 ST D9 F9 7 p 0123 .1.. 0.23 Compute y × log2(x+1) and Pop
GETSEC EAX smx 0F 37 C2++ D20 GETSEC Leaf Functions
GS GS 65 GS segment override prefix
HADDPD xmm xmm/m128 sse3 66 0F 7C r Packed Double-FP Horizontal Add
HADDPS xmm xmm/m128 sse3 F2 0F 7C r Packed Single-FP Horizontal Add
HINT_NOP r/m16/32 0F 18 4 M16 Hintable NOP
HINT_NOP r/m16/32 0F 18 5 M16 Hintable NOP
HINT_NOP r/m16/32 0F 18 6 M16 Hintable NOP
HINT_NOP r/m16/32 0F 18 7 M16 Hintable NOP
HINT_NOP r/m16/32 0F 19 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1A M16 Hintable NOP
HINT_NOP r/m16/32 0F 1B M16 Hintable NOP
HINT_NOP r/m16/32 0F 1C M16 Hintable NOP
HINT_NOP r/m16/32 0F 1D M16 Hintable NOP
HINT_NOP r/m16/32 0F 1E M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 1 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 2 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 3 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 4 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 5 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 6 M16 Hintable NOP
HINT_NOP r/m16/32 0F 1F 7 M16 Hintable NOP
HLT F4 0 Halt
HSUBPD xmm xmm/m128 sse3 66 0F 7D r Packed Double-FP Horizontal Subtract
HSUBPS xmm xmm/m128 sse3 F2 0F 7D r Packed Single-FP Horizontal Subtract
IDIV AL AH AX r/m8 F6 7 o..szapc o..szapc Signed Divide
IDIV rDX rAX r/m16/32/64 F7 7 o..szapc o..szapc Signed Divide
IMUL r16/32/64 r/m16/32/64 imm16/32 69 r o..szapc o......c ...szap. Signed Multiply
IMUL r16/32/64 r/m16/32/64 imm8 6B r o..szapc o......c ...szap. Signed Multiply
IMUL AX AL r/m8 F6 5 o..szapc o......c ...szap. Signed Multiply
IMUL rDX rAX r/m16/32/64 F7 5 o..szapc o......c ...szap. Signed Multiply
IMUL r16/32/64 r/m16/32/64 0F AF r o..szapc o......c ...szap. Signed Multiply
IN AL imm8 E4 f1 Input from Port
IN eAX imm8 E5 f1 Input from Port
IN AL DX EC f1 Input from Port
IN eAX DX ED f1 Input from Port
INC r/m8 FE 0 L o..szap. o..szap. Increment by 1
INC r/m16/32/64 FF 0 L o..szap. o..szap. Increment by 1
INS m8 DX 6C f1 .d...... Input from Port to String
INSB m8 DX
INS m16 DX 6D f1 .d...... Input from Port to String
INSW m16 DX
INS m16/32 DX 6D f1 .d...... Input from Port to String
INSD m32 DX
INSERTPS xmm m32 imm8 sse41 66 0F 3A 21 r C2++ D33 Insert Packed Single-FP Value
INSERTPS xmm xmm imm8
INT 3 eFlags CC f ..i..... ..i..... ..i..... Call to Interrupt Procedure
INT imm8 eFlags CD f ..i..... ..i..... ..i..... Call to Interrupt Procedure
INT1 eFlags F1 U9 ..i..... ..i..... ..i..... Call to Interrupt Procedure
ICEBP eFlags
INTO eFlags CE f o....... ..i..... ..i..... ..i..... Call to Interrupt Procedure
INVD 0F 08 0 Invalidate Internal Caches
INVEPT r64 m128 vmx 66 0F 38 80 r C2++ D32 E 0 o..szapc o..szapc Invalidate Translations Derived from EPT
INVLPG m 0F 01 7 0 Invalidate TLB Entry
INVVPID r64 m128 vmx 66 0F 38 81 r C2++ D32 E 0 o..szapc o..szapc Invalidate Translations Based on VPID
IRET Flags CF E f Interrupt Return
IRETD EFlags
IRETQ RFlags
JB rel8 72 .......c Jump short if below/not above or equal/carry (CF=1)
JNAE rel8
JC rel8
JB rel16/32 0F 82 D31 .......c Jump near if below/not above or equal/carry (CF=1)
JNAE rel16/32
JC rel16/32
JBE rel8 76 ....z..c Jump short if below or equal/not above (CF=1 OR ZF=1)
JNA rel8
JBE rel16/32 0F 86 D31 ....z..c Jump near if below or equal/not above (CF=1 OR ZF=1)
JNA rel16/32
JECXZ rel8 ECX E3 D31 E Jump short if rCX register is 0
JRCXZ rel8 RCX
JL rel8 7C o..s.... Jump short if less/not greater (SF!=OF)
JNGE rel8
JL rel16/32 0F 8C D31 o..s.... Jump near if less/not greater (SF!=OF)
JNGE rel16/32
JLE rel8 7E o..sz... Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel8
JLE rel16/32 0F 8E D31 o..sz... Jump near if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG rel16/32
JMP rel16/32 E9 D31 Jump
JMP rel8 EB Jump
JMP r/m16/32 FF 4 Jump
JMP r/m64 FF 4 D31 E Jump
JMPF m16:16/32/64 FF 5 D12 Jump
JNB rel8 73 .......c Jump short if not below/above or equal/not carry (CF=0)
JAE rel8
JNC rel8
JNB rel16/32 0F 83 D31 .......c Jump near if not below/above or equal/not carry (CF=0)
JAE rel16/32
JNC rel16/32
JNBE rel8 77 ....z..c Jump short if not below or equal/above (CF=0 AND ZF=0)
JA rel8
JNBE rel16/32 0F 87 D31 ....z..c Jump near if not below or equal/above (CF=0 AND ZF=0)
JA rel16/32
JNL rel8 7D o..s.... Jump short if not less/greater or equal (SF=OF)
JGE rel8
JNL rel16/32 0F 8D D31 o..s.... Jump near if not less/greater or equal (SF=OF)
JGE rel16/32
JNLE rel8 7F o..sz... Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel8
JNLE rel16/32 0F 8F D31 o..sz... Jump near if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG rel16/32
JNO rel8 71 o....... Jump short if not overflow (OF=0)
JNO rel16/32 0F 81 D31 o....... Jump near if not overflow (OF=0)
JNP rel8 7B ......p. Jump short if not parity/parity odd (PF=0)
JPO rel8
JNP rel16/32 0F 8B D31 ......p. Jump near if not parity/parity odd (PF=0)
JPO rel16/32
JNS rel8 79 ...s.... Jump short if not sign (SF=0)
JNS rel16/32 0F 89 D31 ...s.... Jump near if not sign (SF=0)
JNZ rel8 75 ....z... Jump short if not zero/not equal (ZF=0)
JNE rel8
JNZ rel16/32 0F 85 D31 ....z... Jump near if not zero/not equal (ZF=0)
JNE rel16/32
JO rel8 70 o....... Jump short if overflow (OF=1)
JO rel16/32 0F 80 D31 o....... Jump near if overflow (OF=1)
JP rel8 7A ......p. Jump short if parity/parity even (PF=1)
JPE rel8
JP rel16/32 0F 8A D31 ......p. Jump near if parity/parity even (PF=1)
JPE rel16/32
JS rel8 78 ...s.... Jump short if sign (SF=1)
JS rel16/32 0F 88 D31 ...s.... Jump near if sign (SF=1)
JZ rel8 74 ....z... Jump short if zero/equal (ZF=1)
JE rel8
JZ rel16/32 0F 84 D31 ....z... Jump near if zero/equal (ZF=1)
JE rel16/32
LAHF AH 9F D2 ...szapc Load Status Flags into AH Register
LAR r16/32/64 m16 0F 02 r P ....z... ....z... Load Access Rights Byte
LAR r16/32/64 r16/32
LDDQU xmm m128 sse3 F2 0F F0 r Load Unaligned Integer 128 Bits
LDMXCSR m32 sse1 0F AE 2 Load MXCSR Register
LEA r16/32/64 m 8D r Load Effective Address
LEAVE rBP C9 E High Level Procedure Exit
LFENCE sse2 0F AE 5 Load Fence
LFS FS r16/32/64 m16:16/32/64 0F B4 r D25 Load Far Pointer
LGDT GDTR m 0F 01 2 0 Load Global Descriptor Table Register
LGS GS r16/32/64 m16:16/32/64 0F B5 r D25 Load Far Pointer
LIDT IDTR m 0F 01 3 0 Load Interrupt Descriptor Table Register
LLDT LDTR r/m16 0F 00 2 P 0 Load Local Descriptor Table Register
LMSW MSW r/m16 0F 01 6 0 Load Machine Status Word
LOCK F0 Assert LOCK# Signal Prefix
LODS AL m8 AC .d...... Load String
LODSB AL m8
LODS rAX m16/32/64 AD E .d...... Load String
LODSW AX m16
LODSD EAX m32
LODSQ RAX m64
LOOP rCX rel8 E2 D31 E Decrement count; Jump short if count!=0
LOOPNZ rCX rel8 E0 D31 E ....z... Decrement count; Jump short if count!=0 and ZF=0
LOOPNE rCX rel8
LOOPZ rCX rel8 E1 D31 E ....z... Decrement count; Jump short if count!=0 and ZF=1
LOOPE rCX rel8
LSL r16/32/64 m16 0F 03 r P ....z... ....z... Load Segment Limit
LSL r16/32/64 r16/32
LSS SS r16/32/64 m16:16/32/64 0F B2 r D25 Load Far Pointer
LTR TR r/m16 0F 00 3 P 0 Load Task Register
MASKMOVDQU m128 xmm xmm sse2 66 0F F7 r Store Selected Bytes of Double Quadword
MASKMOVQ m64 mm mm sse1 0F F7 r D30 Store Selected Bytes of Quadword
MAXPD xmm xmm/m128 sse2 66 0F 5F r Return Maximum Packed Double-FP Values
MAXPS xmm xmm/m128 sse1 0F 5F r Return Maximum Packed Single-FP Values
MAXSD xmm xmm/m64 sse2 F2 0F 5F r Return Maximum Scalar Double-FP Value
MAXSS xmm xmm/m32 sse1 F3 0F 5F r Return Maximum Scalar Single-FP Value
MFENCE sse2 0F AE 6 Memory Fence
MINPD xmm xmm/m128 sse2 66 0F 5D r Return Minimum Packed Double-FP Values
MINPS xmm xmm/m128 sse1 0F 5D r Return Minimum Packed Single-FP Values
MINSD xmm xmm/m64 sse2 F2 0F 5D r Return Minimum Scalar Double-FP Value
MINSS xmm xmm/m32 sse1 F3 0F 5D r Return Minimum Scalar Single-FP Value
MONITOR m8 ECX EDX sse3 0F 01 C8 1 0 Set Up Monitor Address
MOV r/m8 r8 88 r Move
MOV r/m16/32/64 r16/32/64 89 r Move
MOV r8 r/m8 8A r Move
MOV r16/32/64 r/m16/32/64 8B r Move
MOV m16 Sreg 8C r Move
MOV r16/32/64 Sreg
MOV Sreg r/m16 8E r Move
MOV AL moffs8 A0 Move
MOV rAX moffs16/32/64 A1 Move
MOV moffs8 AL A2 Move
MOV moffs16/32/64 rAX A3 Move
MOV r8 imm8 B0+r Move
MOV r16/32/64 imm16/32/64 B8+r Move
MOV r/m8 imm8 C6 0 Move
MOV r/m16/32/64 imm16/32 C7 0 Move
MOV r64 CRn 0F 20 r E 0 o..szapc o..szapc Move to/from Control Registers
MOV r64 CRn 0F 20 r U17 E 0 o..szapc o..szapc Move to/from Control Registers
MOV r64 DRn 0F 21 r E 0 o..szapc o..szapc Move to/from Debug Registers
MOV r64 DRn 0F 21 r U17 E 0 o..szapc o..szapc Move to/from Debug Registers
MOV CRn r64 0F 22 r E 0 o..szapc o..szapc Move to/from Control Registers
MOV CRn r64 0F 22 r U17 E 0 o..szapc o..szapc Move to/from Control Registers
MOV DRn r64 0F 23 r E 0 o..szapc o..szapc Move to/from Debug Registers
MOV DRn r64 0F 23 r U17 E 0 o..szapc o..szapc Move to/from Debug Registers
MOVAPD xmm xmm/m128 sse2 66 0F 28 r Move Aligned Packed Double-FP Values
MOVAPD xmm/m128 xmm sse2 66 0F 29 r Move Aligned Packed Double-FP Values
MOVAPS xmm xmm/m128 sse1 0F 28 r Move Aligned Packed Single-FP Values
MOVAPS xmm/m128 xmm sse1 0F 29 r Move Aligned Packed Single-FP Values
MOVBE r16/32/64 m16/32/64 0F 38 F0 r C2++ Move Data After Swapping Bytes
MOVBE m16/32/64 r16/32/64 0F 38 F1 r C2++ Move Data After Swapping Bytes
MOVD mm r/m32 mmx 0F 6E r D21 E Move Doubleword/Quadword
MOVQ mm r/m64
MOVD xmm r/m32 sse2 66 0F 6E r D21 E Move Doubleword/Quadword
MOVQ xmm r/m64
MOVD r/m32 mm mmx 0F 7E r D21 E Move Doubleword/Quadword
MOVQ r/m64 mm
MOVD r/m32 xmm sse2 66 0F 7E r D21 E Move Doubleword/Quadword
MOVQ r/m64 xmm
MOVDDUP xmm xmm/m64 sse3 F2 0F 12 r Move One Double-FP and Duplicate
MOVDQ2Q mm xmm sse2 F2 0F D6 r Move Quadword from XMM to MMX Technology Register
MOVDQA xmm xmm/m128 sse2 66 0F 6F r Move Aligned Double Quadword
MOVDQA xmm/m128 xmm sse2 66 0F 7F r Move Aligned Double Quadword
MOVDQU xmm xmm/m128 sse2 F3 0F 6F r Move Unaligned Double Quadword
MOVDQU xmm/m128 xmm sse2 F3 0F 7F r Move Unaligned Double Quadword
MOVHLPS xmm xmm sse1 0F 12 r Move Packed Single-FP Values High to Low
MOVHPD xmm m64 sse2 66 0F 16 r Move High Packed Double-FP Value
MOVHPD m64 xmm sse2 66 0F 17 r Move High Packed Double-FP Value
MOVHPS xmm m64 sse1 0F 16 r Move High Packed Single-FP Values
MOVHPS m64 xmm sse1 0F 17 r Move High Packed Single-FP Values
MOVLHPS xmm xmm sse1 0F 16 r Move Packed Single-FP Values Low to High
MOVLPD xmm m64 sse2 66 0F 12 r Move Low Packed Double-FP Value
MOVLPD m64 xmm sse2 66 0F 13 r Move Low Packed Double-FP Value
MOVLPS xmm m64 sse1 0F 12 r Move Low Packed Single-FP Values
MOVLPS m64 xmm sse1 0F 13 r Move Low Packed Single-FP Values
MOVMSKPD r32/64 xmm sse2 66 0F 50 r Extract Packed Double-FP Sign Mask
MOVMSKPS r32/64 xmm sse1 0F 50 r Extract Packed Single-FP Sign Mask
MOVNTDQ m128 xmm sse2 66 0F E7 r Store Double Quadword Using Non-Temporal Hint
MOVNTI m32/64 r32/64 sse2 0F C3 r Store Doubleword Using Non-Temporal Hint
MOVNTPD m128 xmm sse2 66 0F 2B r Store Packed Double-FP Values Using Non-Temporal Hint
MOVNTPS m128 xmm sse1 0F 2B r Store Packed Single-FP Values Using Non-Temporal Hint
MOVNTQ m64 mm sse1 0F E7 r Store of Quadword Using Non-Temporal Hint
MOVQ mm mm/m64 mmx 0F 6F r Move Quadword
MOVQ xmm xmm/m64 sse2 F3 0F 7E r Move Quadword
MOVQ mm/m64 mm mmx 0F 7F r Move Quadword
MOVQ xmm/m64 xmm sse2 66 0F D6 r Move Quadword
MOVQ2DQ xmm mm sse2 F3 0F D6 r Move Quadword from MMX Technology to XMM Register
MOVS m8 m8 A4 .d...... Move Data from String to String
MOVSB m8 m8
MOVS m16/32/64 m16/32/64 A5 E .d...... Move Data from String to String
MOVSW m16 m16
MOVSD m32 m32
MOVSQ m64 m64
MOVSD xmm xmm/m64 sse2 F2 0F 10 r Move Scalar Double-FP Value
MOVSD xmm/m64 xmm sse2 F2 0F 11 r Move Scalar Double-FP Value
MOVSHDUP xmm xmm/m64 sse3 F3 0F 16 r Move Packed Single-FP High and Duplicate
MOVSLDUP xmm xmm/m64 sse3 F3 0F 12 r Move Packed Single-FP Low and Duplicate
MOVSS xmm xmm/m32 sse1 F3 0F 10 r Move Scalar Single-FP Values
MOVSS xmm/m32 xmm sse1 F3 0F 11 r Move Scalar Single-FP Values
MOVSX r16/32/64 r/m8 0F BE r Move with Sign-Extension
MOVSX r16/32/64 r/m16 0F BF r Move with Sign-Extension
MOVSXD r32/64 r/m32 63 r E Move with Sign-Extension
MOVUPD xmm xmm/m128 sse2 66 0F 10 r Move Unaligned Packed Double-FP Value
MOVUPD xmm/m128 xmm sse2 66 0F 11 r Move Unaligned Packed Double-FP Values
MOVUPS xmm xmm/m128 sse1 0F 10 r Move Unaligned Packed Single-FP Values
MOVUPS xmm/m128 xmm sse1 0F 11 r Move Unaligned Packed Single-FP Values
MOVZX r16/32/64 r/m8 0F B6 r Move with Zero-Extend
MOVZX r16/32/64 r/m16 0F B7 r Move with Zero-Extend
MPSADBW xmm xmm/m128 imm8 sse41 66 0F 3A 42 r C2++ D33 Compute Multiple Packed Sums of Absolute Difference
MUL AX AL r/m8 F6 4 o..szapc o......c ...szap. Unsigned Multiply
MUL rDX rAX r/m16/32/64 F7 4 o..szapc o......c ...szap. Unsigned Multiply
MULPD xmm xmm/m128 sse2 66 0F 59 r Multiply Packed Double-FP Values
MULPS xmm xmm/m128 sse1 0F 59 r Multiply Packed Single-FP Values
MULSD xmm xmm/m64 sse2 F2 0F 59 r Multiply Scalar Double-FP Values
MULSS xmm xmm/m32 sse1 F3 0F 59 r Multiply Scalar Single-FP Value
MWAIT EAX ECX sse3 0F 01 C9 1 0 Monitor Wait
NEG r/m8 F6 3 L o..szapc o..szapc Two's Complement Negation
NEG r/m16/32/64 F7 3 L o..szapc o..szapc Two's Complement Negation
NOP 90 D1 No Operation
NOP r/m16/32 0F 0D M15 No Operation
NOP r/m16/32 0F 1F 0 No Operation
NOT r/m8 F6 2 L One's Complement Negation
NOT r/m16/32/64 F7 2 L One's Complement Negation
OR r/m8 r8 08 r L o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r/m16/32/64 r16/32/64 09 r L o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r8 r/m8 0A r o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r16/32/64 r/m16/32/64 0B r o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR AL imm8 0C o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR rAX imm16/32 0D o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r/m8 imm8 80 1 L o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r/m16/32/64 imm16/32 81 1 L o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR r/m16/32/64 imm8 83 1 L o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
ORPD xmm xmm/m128 sse2 66 0F 56 r Bitwise Logical OR of Double-FP Values
ORPS xmm xmm/m128 sse1 0F 56 r Bitwise Logical OR of Single-FP Values
OUT imm8 AL E6 f1 Output to Port
OUT imm8 eAX E7 f1 Output to Port
OUT DX AL EE f1 Output to Port
OUT DX eAX EF f1 Output to Port
OUTS DX m8 6E f1 .d...... Output String to Port
OUTSB DX m8
OUTS DX m16 6F f1 .d...... Output String to Port
OUTSW DX m16
OUTS DX m16/32 6F f1 .d...... Output String to Port
OUTSD DX m32
PACKSSDW mm mm/m64 mmx 0F 6B r Pack with Signed Saturation
PACKSSDW xmm xmm/m128 sse2 66 0F 6B r Pack with Signed Saturation
PACKSSWB mm mm/m64 mmx 0F 63 r Pack with Signed Saturation
PACKSSWB xmm xmm/m128 sse2 66 0F 63 r Pack with Signed Saturation
PACKUSWB mm mm/m64 mmx 0F 67 r Pack with Unsigned Saturation
PACKUSWB xmm xmm/m128 sse2 66 0F 67 r Pack with Unsigned Saturation
PADDB mm mm/m64 mmx 0F FC r Add Packed Integers
PADDB xmm xmm/m128 sse2 66 0F FC r Add Packed Integers
PADDD mm mm/m64 mmx 0F FE r Add Packed Integers
PADDD xmm xmm/m128 sse2 66 0F FE r Add Packed Integers
PADDQ mm mm/m64 sse2 0F D4 r Add Packed Quadword Integers
PADDQ xmm xmm/m128 sse2 66 0F D4 r Add Packed Quadword Integers
PADDSB mm mm/m64 mmx 0F EC r Add Packed Signed Integers with Signed Saturation
PADDSB xmm xmm/m128 sse2 66 0F EC r Add Packed Signed Integers with Signed Saturation
PADDSW mm mm/m64 mmx 0F ED r Add Packed Signed Integers with Signed Saturation
PADDSW xmm xmm/m128 sse2 66 0F ED r Add Packed Signed Integers with Signed Saturation
PADDUSB mm mm/m64 mmx 0F DC r Add Packed Unsigned Integers with Unsigned Saturation
PADDUSB xmm xmm/m128 sse2 66 0F DC r Add Packed Unsigned Integers with Unsigned Saturation
PADDUSW mm mm/m64 mmx 0F DD r Add Packed Unsigned Integers with Unsigned Saturation
PADDUSW xmm xmm/m128 sse2 66 0F DD r Add Packed Unsigned Integers with Unsigned Saturation
PADDW mm mm/m64 mmx 0F FD r Add Packed Integers
PADDW xmm xmm/m128 sse2 66 0F FD r Add Packed Integers
PALIGNR mm mm/m64 ssse3 0F 3A 0F r C2+ Packed Align Right
PALIGNR xmm xmm/m128 ssse3 66 0F 3A 0F r C2+ Packed Align Right
PAND mm mm/m64 mmx 0F DB r Logical AND
PAND xmm xmm/m128 sse2 66 0F DB r Logical AND
PANDN mm mm/m64 mmx 0F DF r Logical AND NOT
PANDN xmm xmm/m128 sse2 66 0F DF r Logical AND NOT
PAUSE sse2 F3 90 Spin Loop Hint
PAVGB mm mm/m64 sse1 0F E0 r Average Packed Integers
PAVGB xmm xmm/m128 sse1 66 0F E0 r Average Packed Integers
PAVGW mm mm/m64 sse1 0F E3 r Average Packed Integers
PAVGW xmm xmm/m128 sse1 66 0F E3 r Average Packed Integers
PBLENDW xmm xmm/m128 imm8 sse41 66 0F 3A 0E r C2++ D33 Blend Packed Words
PCMPEQB mm mm/m64 mmx 0F 74 r Compare Packed Data for Equal
PCMPEQB xmm xmm/m128 sse2 66 0F 74 r Compare Packed Data for Equal
PCMPEQD mm mm/m64 mmx 0F 76 r Compare Packed Data for Equal
PCMPEQD xmm xmm/m128 sse2 66 0F 76 r Compare Packed Data for Equal
PCMPEQW mm mm/m64 mmx 0F 75 r Compare Packed Data for Equal
PCMPEQW xmm xmm/m128 sse2 66 0F 75 r Compare Packed Data for Equal
PCMPESTRI rCX xmm xmm/m128 ... sse42 66 0F 3A 61 r C2++ D33 o..szapc o..szapc .....ap. Packed Compare Explicit Length Strings, Return Index
PCMPESTRM XMM0 xmm xmm/m128 ... sse42 66 0F 3A 60 r C2++ D33 o..szapc o..szapc .....ap. Packed Compare Explicit Length Strings, Return Mask
PCMPGTB mm mm/m64 mmx 0F 64 r Compare Packed Signed Integers for Greater Than
PCMPGTB xmm xmm/m128 sse2 66 0F 64 r Compare Packed Signed Integers for Greater Than
PCMPGTD mm mm/m64 mmx 0F 66 r Compare Packed Signed Integers for Greater Than
PCMPGTD xmm xmm/m128 sse2 66 0F 66 r Compare Packed Signed Integers for Greater Than
PCMPGTW mm mm/m64 mmx 0F 65 r Compare Packed Signed Integers for Greater Than
PCMPGTW xmm xmm/m128 sse2 66 0F 65 r Compare Packed Signed Integers for Greater Than
PCMPISTRI rCX xmm xmm/m128 imm8 sse42 66 0F 3A 63 r C2++ D33 o..szapc o..szapc .....ap. Packed Compare Implicit Length Strings, Return Index
PCMPISTRM XMM0 xmm xmm/m128 imm8 sse42 66 0F 3A 62 r C2++ D33 o..szapc o..szapc .....ap. Packed Compare Implicit Length Strings, Return Mask
PEXTRB m8 xmm imm8 sse41 66 0F 3A 14 r C2++ D33 Extract Byte
PEXTRB r32/64 xmm imm8
PEXTRD r/m32 xmm imm8 sse41 66 0F 3A 16 r C2++ D33 Extract Dword/Qword
PEXTRQ r/m64 xmm imm8
PEXTRW m16 xmm imm8 sse41 66 0F 3A 15 r C2++ D33 Extract Word
PEXTRW r32/64 xmm imm8
PEXTRW r32/64 mm imm8 sse1 0F C5 r Extract Word
PEXTRW r32/64 xmm imm8 sse1 66 0F C5 r Extract Word
PINSRB xmm m8 imm8 sse41 66 0F 3A 20 r C2++ D33 Insert Byte
PINSRB xmm r32/64 imm8
PINSRD xmm r/m32 imm8 sse41 66 0F 3A 22 r C2++ D33 Insert Dword/Qword
PINSRQ xmm r/m64 imm8
PINSRW mm r32/64 imm8 sse1 0F C4 r Insert Word
PINSRW mm m16 imm8
PINSRW xmm r32/64 imm8 sse1 66 0F C4 r Insert Word
PINSRW xmm m16 imm8
PMADDWD mm mm/m64 mmx 0F F5 r Multiply and Add Packed Integers
PMADDWD xmm xmm/m128 sse2 66 0F F5 r Multiply and Add Packed Integers
PMAXSW mm mm/m64 sse1 0F EE r Maximum of Packed Signed Word Integers
PMAXSW xmm xmm/m128 sse1 66 0F EE r Maximum of Packed Signed Word Integers
PMAXUB mm mm/m64 sse1 0F DE r Maximum of Packed Unsigned Byte Integers
PMAXUB xmm xmm/m128 sse1 66 0F DE r Maximum of Packed Unsigned Byte Integers
PMINSW mm mm/m64 sse1 0F EA r Minimum of Packed Signed Word Integers
PMINSW xmm xmm/m128 sse1 66 0F EA r Minimum of Packed Signed Word Integers
PMINUB mm mm/m64 sse1 0F DA r Minimum of Packed Unsigned Byte Integers
PMINUB xmm xmm/m128 sse1 66 0F DA r Minimum of Packed Unsigned Byte Integers
PMOVMSKB r32/64 mm sse1 0F D7 r Move Byte Mask
PMOVMSKB r32/64 xmm sse1 66 0F D7 r Move Byte Mask
PMULHUW mm mm/m64 sse1 0F E4 r Multiply Packed Unsigned Integers and Store High Result
PMULHUW xmm xmm/m128 sse1 66 0F E4 r Multiply Packed Unsigned Integers and Store High Result
PMULHW mm mm/m64 mmx 0F E5 r Multiply Packed Signed Integers and Store High Result
PMULHW xmm xmm/m128 sse2 66 0F E5 r Multiply Packed Signed Integers and Store High Result
PMULLW mm mm/m64 mmx 0F D5 r Multiply Packed Signed Integers and Store Low Result
PMULLW xmm xmm/m128 sse2 66 0F D5 r Multiply Packed Signed Integers and Store Low Result
PMULUDQ mm mm/m64 sse2 0F F4 r Multiply Packed Unsigned DW Integers
PMULUDQ xmm xmm/m128 sse2 66 0F F4 r Multiply Packed Unsigned DW Integers
POP r64/16 58+r E Pop a Value from the Stack
POP r/m16/32 8F 0 Pop a Value from the Stack
POP r/m64/16 8F 0 E Pop a Value from the Stack
POP FS 0F A1 Pop a Value from the Stack
POP GS 0F A9 Pop a Value from the Stack
POPCNT r16/32/64 r/m16/32/64 F3 0F B8 r C2++ o..szapc o..s.apc Bit Population Count
POPF Flags 9D E Pop Stack into rFLAGS Register
POPFQ RFlags
POR mm mm/m64 mmx 0F EB r Bitwise Logical OR
POR xmm xmm/m128 sse2 66 0F EB r Bitwise Logical OR
PREFETCHNTA m8 sse1 0F 18 0 Prefetch Data Into Caches
PREFETCHT0 m8 sse1 0F 18 1 Prefetch Data Into Caches
PREFETCHT1 m8 sse1 0F 18 2 Prefetch Data Into Caches
PREFETCHT2 m8 sse1 0F 18 3 Prefetch Data Into Caches
PSADBW mm mm/m64 sse1 0F F6 r Compute Sum of Absolute Differences
PSADBW xmm xmm/m128 sse1 66 0F F6 r Compute Sum of Absolute Differences
PSHUFD xmm xmm/m128 imm8 sse2 66 0F 70 r Shuffle Packed Doublewords
PSHUFHW xmm xmm/m128 imm8 sse2 F3 0F 70 r Shuffle Packed High Words
PSHUFLW xmm xmm/m128 imm8 sse2 F2 0F 70 r Shuffle Packed Low Words
PSHUFW mm mm/m64 imm8 sse1 0F 70 r Shuffle Packed Words
PSLLD mm imm8 mmx 0F 72 6 Shift Packed Data Left Logical
PSLLD xmm imm8 sse2 66 0F 72 6 Shift Packed Data Left Logical
PSLLD mm mm/m64 mmx 0F F2 r Shift Packed Data Left Logical
PSLLD xmm xmm/m128 sse2 66 0F F2 r Shift Packed Data Left Logical
PSLLDQ xmm imm8 sse2 66 0F 73 7 Shift Double Quadword Left Logical
PSLLQ mm imm8 mmx 0F 73 6 Shift Packed Data Left Logical
PSLLQ xmm imm8 sse2 66 0F 73 6 Shift Packed Data Left Logical
PSLLQ mm mm/m64 mmx 0F F3 r Shift Packed Data Left Logical
PSLLQ xmm xmm/m128 sse2 66 0F F3 r Shift Packed Data Left Logical
PSLLW mm imm8 mmx 0F 71 6 Shift Packed Data Left Logical
PSLLW xmm imm8 sse2 66 0F 71 6 Shift Packed Data Left Logical
PSLLW mm mm/m64 mmx 0F F1 r Shift Packed Data Left Logical
PSLLW xmm xmm/m128 sse2 66 0F F1 r Shift Packed Data Left Logical
PSRAD mm imm8 mmx 0F 72 4 Shift Packed Data Right Arithmetic
PSRAD xmm imm8 sse2 66 0F 72 4 Shift Packed Data Right Arithmetic
PSRAD mm mm/m64 mmx 0F E2 r Shift Packed Data Right Arithmetic
PSRAD xmm xmm/m128 sse2 66 0F E2 r Shift Packed Data Right Arithmetic
PSRAW mm imm8 mmx 0F 71 4 Shift Packed Data Right Arithmetic
PSRAW xmm imm8 sse2 66 0F 71 4 Shift Packed Data Right Arithmetic
PSRAW mm mm/m64 mmx 0F E1 r Shift Packed Data Right Arithmetic
PSRAW xmm xmm/m128 sse2 66 0F E1 r Shift Packed Data Right Arithmetic
PSRLD mm imm8 mmx 0F 72 2 Shift Double Quadword Right Logical
PSRLD xmm imm8 sse2 66 0F 72 2 Shift Double Quadword Right Logical
PSRLD mm mm/m64 mmx 0F D2 r Shift Packed Data Right Logical
PSRLD xmm xmm/m128 sse2 66 0F D2 r Shift Packed Data Right Logical
PSRLDQ xmm imm8 sse2 66 0F 73 3 Shift Double Quadword Right Logical
PSRLQ mm imm8 mmx 0F 73 2 Shift Packed Data Right Logical
PSRLQ xmm imm8 sse2 66 0F 73 2 Shift Packed Data Right Logical
PSRLQ mm mm/m64 mmx 0F D3 r Shift Packed Data Right Logical
PSRLQ xmm xmm/m128 sse2 66 0F D3 r Shift Packed Data Right Logical
PSRLW mm imm8 mmx 0F 71 2 Shift Packed Data Right Logical
PSRLW xmm imm8 sse2 66 0F 71 2 Shift Packed Data Right Logical
PSRLW mm mm/m64 mmx 0F D1 r Shift Packed Data Right Logical
PSRLW xmm xmm/m128 sse2 66 0F D1 r Shift Packed Data Right Logical
PSUBB mm mm/m64 mmx 0F F8 r Subtract Packed Integers
PSUBB xmm xmm/m128 sse2 66 0F F8 r Subtract Packed Integers
PSUBD mm mm/m64 mmx 0F FA r Subtract Packed Integers
PSUBD xmm xmm/m128 sse2 66 0F FA r Subtract Packed Integers
PSUBQ mm mm/m64 sse2 0F FB r Subtract Packed Quadword Integers
PSUBQ xmm xmm/m128 sse2 66 0F FB r Subtract Packed Quadword Integers
PSUBSB mm mm/m64 mmx 0F E8 r Subtract Packed Signed Integers with Signed Saturation
PSUBSB xmm xmm/m128 sse2 66 0F E8 r Subtract Packed Signed Integers with Signed Saturation
PSUBSW mm mm/m64 mmx 0F E9 r Subtract Packed Signed Integers with Signed Saturation
PSUBSW xmm xmm/m128 sse2 66 0F E9 r Subtract Packed Signed Integers with Signed Saturation
PSUBUSB mm mm/m64 mmx 0F D8 r Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSB xmm xmm/m128 sse2 66 0F D8 r Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSW mm mm/m64 mmx 0F D9 r Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSW xmm xmm/m128 sse2 66 0F D9 r Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBW mm mm/m64 mmx 0F F9 r Subtract Packed Integers
PSUBW xmm xmm/m128 sse2 66 0F F9 r Subtract Packed Integers
PUNPCKHBW mm mm/m64 mmx 0F 68 r Unpack High Data
PUNPCKHBW xmm xmm/m128 sse2 66 0F 68 r Unpack High Data
PUNPCKHDQ mm mm/m64 mmx 0F 6A r Unpack High Data
PUNPCKHDQ xmm xmm/m128 sse2 66 0F 6A r Unpack High Data
PUNPCKHQDQ xmm xmm/m128 sse2 66 0F 6D r Unpack High Data
PUNPCKHWD mm mm/m64 mmx 0F 69 r Unpack High Data
PUNPCKHWD xmm xmm/m128 sse2 66 0F 69 r Unpack High Data
PUNPCKLBW mm mm/m64 mmx 0F 60 r Unpack Low Data
PUNPCKLBW xmm xmm/m128 sse2 66 0F 60 r Unpack Low Data
PUNPCKLDQ mm mm/m64 mmx 0F 62 r Unpack Low Data
PUNPCKLDQ xmm xmm/m128 sse2 66 0F 62 r Unpack Low Data
PUNPCKLQDQ xmm xmm/m128 sse2 66 0F 6C r Unpack Low Data
PUNPCKLWD mm mm/m64 mmx 0F 61 r Unpack Low Data
PUNPCKLWD xmm xmm/m128 sse2 66 0F 61 r Unpack Low Data
PUSH r64/16 50+r E Push Word, Doubleword or Quadword Onto the Stack
PUSH imm16/32 68 Push Word, Doubleword or Quadword Onto the Stack
PUSH imm8 6A Push Word, Doubleword or Quadword Onto the Stack
PUSH r/m16/32 FF 6 Push Word, Doubleword or Quadword Onto the Stack
PUSH r/m64/16 FF 6 E Push Word, Doubleword or Quadword Onto the Stack
PUSH FS 0F A0 Push Word, Doubleword or Quadword Onto the Stack
PUSH GS 0F A8 Push Word, Doubleword or Quadword Onto the Stack
PUSHF Flags 9C E Push rFLAGS Register onto the Stack
PUSHFQ RFlags
PXOR mm mm/m64 mmx 0F EF r Logical Exclusive OR
PXOR xmm xmm/m128 sse2 66 0F EF r Logical Exclusive OR
RCL r/m8 imm8 C0 2 .......c o..szapc o..szapc o....... Rotate
RCL r/m16/32/64 imm8 C1 2 .......c o..szapc o..szapc o....... Rotate
RCL r/m8 1 D0 2 .......c o..szapc o..szapc Rotate
RCL r/m16/32/64 1 D1 2 .......c o..szapc o..szapc Rotate
RCL r/m8 CL D2 2 .......c o..szapc o..szapc o....... Rotate
RCL r/m16/32/64 CL D3 2 .......c o..szapc o..szapc o....... Rotate
RCPPS xmm xmm/m128 sse1 0F 53 r Compute Reciprocals of Packed Single-FP Values
RCPSS xmm xmm/m32 sse1 F3 0F 53 r Compute Reciprocal of Scalar Single-FP Values
RCR r/m8 imm8 C0 3 .......c o..szapc o..szapc o....... Rotate
RCR r/m16/32/64 imm8 C1 3 .......c o..szapc o..szapc o....... Rotate
RCR r/m8 1 D0 3 .......c o..szapc o..szapc Rotate
RCR r/m16/32/64 1 D1 3 .......c o..szapc o..szapc Rotate
RCR r/m8 CL D2 3 .......c o..szapc o..szapc o....... Rotate
RCR r/m16/32/64 CL D3 3 .......c o..szapc o..szapc o....... Rotate
RDMSR rAX rDX rCX MSR 0F 32 0 Read from Model Specific Register
RDPMC EAX EDX PMC 0F 33 f3 Read Performance-Monitoring Counters
RDTSC EAX EDX IA32_TIME_S… 0F 31 f2 Read Time-Stamp Counter
RDTSCP EAX EDX ECX ... 0F 01 F9 7 C7+ f2 Read Time-Stamp Counter and Processor ID
REP rCX F2 U10 E Repeat String Operation Prefix
REP rCX F3 D10 E Repeat String Operation Prefix
REPNZ rCX F2 D10 E ....z... Repeat String Operation Prefix
REPNE rCX
REPZ rCX F3 D10 E ....z... Repeat String Operation Prefix
REPE rCX
RETF imm16 CA f Return from procedure
RETF CB f Return from procedure
RETN imm16 C2 Return from procedure
RETN C3 Return from procedure
REX 40 E Access to new 8-bit registers
REX.B 41 E Extension of r/m field, base field, or opcode reg field
REX.R 44 E Extension of ModR/M reg field
REX.RB 45 E REX.R and REX.B combination
REX.RX 46 E REX.R and REX.X combination
REX.RXB 47 E REX.R, REX.X and REX.B combination
REX.W 48 E 64 Bit Operand Size
REX.WB 49 E REX.W and REX.B combination
REX.WR 4C E REX.W and REX.R combination
REX.WRB 4D E REX.W, REX.R and REX.B combination
REX.WRX 4E E REX.W, REX.R and REX.X combination
REX.WRXB 4F E REX.W, REX.R, REX.X and REX.B combination
REX.WX 4A E REX.W and REX.X combination
REX.WXB 4B E REX.W, REX.X and REX.B combination
REX.X 42 E Extension of SIB index field
REX.XB 43 E REX.X and REX.B combination
ROL r/m8 imm8 C0 0 o..szapc o..szapc o....... Rotate
ROL r/m16/32/64 imm8 C1 0 o..szapc o..szapc o....... Rotate
ROL r/m8 1 D0 0 o..szapc o..szapc Rotate
ROL r/m16/32/64 1 D1 0 o..szapc o..szapc Rotate
ROL r/m8 CL D2 0 o..szapc o..szapc o....... Rotate
ROL r/m16/32/64 CL D3 0 o..szapc o..szapc o....... Rotate
ROR r/m8 imm8 C0 1 o..szapc o..szapc o....... Rotate
ROR r/m16/32/64 imm8 C1 1 o..szapc o..szapc o....... Rotate
ROR r/m8 1 D0 1 o..szapc o..szapc Rotate
ROR r/m16/32/64 1 D1 1 o..szapc o..szapc Rotate
ROR r/m8 CL D2 1 o..szapc o..szapc o....... Rotate
ROR r/m16/32/64 CL D3 1 o..szapc o..szapc o....... Rotate
ROUNDPD xmm xmm/m128 imm8 sse41 66 0F 3A 09 r C2++ D33 Round Packed Double-FP Values
ROUNDPS xmm xmm/m128 imm8 sse41 66 0F 3A 08 r C2++ D33 Round Packed Single-FP Values
ROUNDSD xmm xmm/m64 imm8 sse41 66 0F 3A 0B r C2++ D33 Round Scalar Double-FP Values
ROUNDSS xmm xmm/m32 imm8 sse41 66 0F 3A 0A r C2++ D33 Round Scalar Single-FP Values
RSM Flags 0F AA S Resume from System Management Mode
RSQRTPS xmm xmm/m128 sse1 0F 52 r Compute Recipr. of Square Roots of Packed Single-FP Values
RSQRTSS xmm xmm/m32 sse1 F3 0F 52 r Compute Recipr. of Square Root of Scalar Single-FP Value
SAHF AH 9E D2 ...szapc ...szapc Store AH into Flags
SAL r/m8 imm8 C0 6 U3 o..szapc o..sz.pc o....a.c Shift
SHL r/m8 imm8
SAL r/m16/32/64 imm8 C1 6 U3 o..szapc o..sz.pc o....a.c Shift
SHL r/m16/32/64 imm8
SAL r/m8 1 D0 6 U3 o..szapc o..sz.pc .....a.. Shift
SHL r/m8 1
SAL r/m16/32/64 1 D1 6 U3 o..szapc o..sz.pc .....a.. Shift
SHL r/m16/32/64 1
SAL r/m8 CL D2 6 U3 o..szapc o..sz.pc o....a.c Shift
SHL r/m8 CL
SAL r/m16/32/64 CL D3 6 U3 o..szapc o..sz.pc o....a.c Shift
SHL r/m16/32/64 CL
SAR r/m8 imm8 C0 7 o..szapc o..sz.pc o....a.. Shift
SAR r/m16/32/64 imm8 C1 7 o..szapc o..sz.pc o....a.. Shift
SAR r/m8 1 D0 7 o..szapc o..sz.pc .....a.. Shift
SAR r/m16/32/64 1 D1 7 o..szapc o..sz.pc .....a.. Shift
SAR r/m8 CL D2 7 o..szapc o..sz.pc o....a.. Shift
SAR r/m16/32/64 CL D3 7 o..szapc o..sz.pc .....a.. Shift
SBB r/m8 r8 18 r L .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r/m16/32/64 r16/32/64 19 r L .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r8 r/m8 1A r .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r16/32/64 r/m16/32/64 1B r .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB AL imm8 1C .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB rAX imm16/32 1D .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r/m8 imm8 80 3 L .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r/m16/32/64 imm16/32 81 3 L .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB r/m16/32/64 imm8 83 3 L .......c o..szapc o..szapc Integer Subtraction with Borrow
SCAS m8 AL AE .d...... o..szapc o..szapc Scan String
SCASB m8 AL
SCAS m16/32/64 rAX AF E .d...... o..szapc o..szapc Scan String
SCASW m16 AX
SCASD m32 EAX
SCASQ m64 RAX
SETB r/m8 0F 92 0 D23 .......c Set Byte on Condition - below/not above or equal/carry (CF=1)
SETNAE r/m8
SETC r/m8
SETBE r/m8 0F 96 0 D23 ....z..c Set Byte on Condition - below or equal/not above (CF=1 OR ZF=1)
SETNA r/m8
SETL r/m8 0F 9C 0 D23 o..s.... Set Byte on Condition - less/not greater (SF!=OF)
SETNGE r/m8
SETLE r/m8 0F 9E 0 D23 o..sz... Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNG r/m8
SETNB r/m8 0F 93 0 D23 .......c Set Byte on Condition - not below/above or equal/not carry (CF=0)
SETAE r/m8
SETNC r/m8
SETNBE r/m8 0F 97 0 D23 ....z..c Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETA r/m8
SETNL r/m8 0F 9D 0 D23 o..s.... Set Byte on Condition - not less/greater or equal (SF=OF)
SETGE r/m8
SETNLE r/m8 0F 9F 0 D23 o..sz... Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETG r/m8
SETNO r/m8 0F 91 0 D23 o....... Set Byte on Condition - not overflow (OF=0)
SETNP r/m8 0F 9B 0 D23 ......p. Set Byte on Condition - not parity/parity odd (PF=0)
SETPO r/m8
SETNS r/m8 0F 99 0 D23 ...s.... Set Byte on Condition - not sign (SF=0)
SETNZ r/m8 0F 95 0 D23 ....z... Set Byte on Condition - not zero/not equal (ZF=0)
SETNE r/m8
SETO r/m8 0F 90 0 D23 o....... Set Byte on Condition - overflow (OF=1)
SETP r/m8 0F 9A 0 D23 ......p. Set Byte on Condition - parity/parity even (PF=1)
SETPE r/m8
SETS r/m8 0F 98 0 D23 ...s.... Set Byte on Condition - sign (SF=1)
SETZ r/m8 0F 94 0 D23 ....z... Set Byte on Condition - zero/equal (ZF=1)
SETE r/m8
SFENCE sse1 0F AE 7 Store Fence
SGDT m GDTR 0F 01 0 Store Global Descriptor Table Register
SHL r/m8 imm8 C0 4 o..szapc o..sz.pc o....a.c Shift
SAL r/m8 imm8
SHL r/m16/32/64 imm8 C1 4 o..szapc o..sz.pc o....a.c Shift
SAL r/m16/32/64 imm8
SHL r/m8 1 D0 4 o..szapc o..sz.pc .....a.. Shift
SAL r/m8 1
SHL r/m16/32/64 1 D1 4 o..szapc o..sz.pc .....a.. Shift
SAL r/m16/32/64 1
SHL r/m8 CL D2 4 o..szapc o..sz.pc o....a.c Shift
SAL r/m8 CL
SHL r/m16/32/64 CL D3 4 o..szapc o..sz.pc o....a.c Shift
SAL r/m16/32/64 CL
SHLD r/m16/32/64 r16/32/64 imm8 0F A4 r o..szapc o..sz.pc o....a.c Double Precision Shift Left
SHLD r/m16/32/64 r16/32/64 CL 0F A5 r o..szapc o..sz.pc o....a.c Double Precision Shift Left
SHR r/m8 imm8 C0 5 o..szapc o..sz.pc o....a.c Shift
SHR r/m16/32/64 imm8 C1 5 o..szapc o..sz.pc o....a.c Shift
SHR r/m8 1 D0 5 o..szapc o..sz.pc .....a.. Shift
SHR r/m16/32/64 1 D1 5 o..szapc o..sz.pc .....a.. Shift
SHR r/m8 CL D2 5 o..szapc o..sz.pc o....a.c Shift
SHR r/m16/32/64 CL D3 5 o..szapc o..sz.pc o....a.c Shift
SHRD r/m16/32/64 r16/32/64 imm8 0F AC r o..szapc o..sz.pc o....a.c Double Precision Shift Right
SHRD r/m16/32/64 r16/32/64 CL 0F AD r o..szapc o..sz.pc o....a.c Double Precision Shift Right
SHUFPD xmm xmm/m128 imm8 sse2 66 0F C6 r Shuffle Packed Double-FP Values
SHUFPS xmm xmm/m128 imm8 sse1 0F C6 r Shuffle Packed Single-FP Values
SIDT m IDTR 0F 01 1 Store Interrupt Descriptor Table Register
SLDT m16 LDTR 0F 00 0 P Store Local Descriptor Table Register
SLDT r16/32/64 LDTR
SMSW m16 MSW 0F 01 4 D13 Store Machine Status Word
SMSW r16/32/64 MSW
SQRTPD xmm xmm/m128 sse2 66 0F 51 r Compute Square Roots of Packed Double-FP Values
SQRTPS xmm xmm/m128 sse1 0F 51 r Compute Square Roots of Packed Single-FP Values
SQRTSD xmm xmm/m64 sse2 F2 0F 51 r Compute Square Root of Scalar Double-FP Value
SQRTSS xmm xmm/m32 sse1 F3 0F 51 r Compute Square Root of Scalar Single-FP Value
STC F9 .......c .......c .......C Set Carry Flag
STD FD .d...... .d...... .D...... Set Direction Flag
STI FB f1 ..i..... ..i..... ..I..... Set Interrupt Flag
STMXCSR m32 sse1 0F AE 3 Store MXCSR Register State
STOS m8 AL AA .d...... Store String
STOSB m8 AL
STOS m16/32/64 rAX AB E .d...... Store String
STOSW m16 AX
STOSD m32 EAX
STOSQ m64 RAX
STR m16 TR 0F 00 1 P Store Task Register
STR r16/32/64 TR
SUB r/m8 r8 28 r L o..szapc o..szapc Subtract
SUB r/m16/32/64 r16/32/64 29 r L o..szapc o..szapc Subtract
SUB r8 r/m8 2A r o..szapc o..szapc Subtract
SUB r16/32/64 r/m16/32/64 2B r o..szapc o..szapc Subtract
SUB AL imm8 2C o..szapc o..szapc Subtract
SUB rAX imm16/32 2D o..szapc o..szapc Subtract
SUB r/m8 imm8 80 5 L o..szapc o..szapc Subtract
SUB r/m16/32/64 imm16/32 81 5 L o..szapc o..szapc Subtract
SUB r/m16/32/64 imm8 83 5 L o..szapc o..szapc Subtract
SUBPD xmm xmm/m128 sse2 66 0F 5C r Subtract Packed Double-FP Values
SUBPS xmm xmm/m128 sse1 0F 5C r Subtract Packed Single-FP Values
SUBSD xmm xmm/m64 sse2 F2 0F 5C r Subtract Scalar Double-FP Values
SUBSS xmm xmm/m32 sse1 F3 0F 5C r Subtract Scalar Single-FP Values
SWAPGS GS IA32_KERNEL_… 0F 01 F8 7 E 0 Swap GS Base Register
SYSCALL RCX R11 SS ... 0F 05 D14 E Fast System Call
SYSENTER SS RSP IA32_SYSENT… ... 0F 34 D18 E ..i..... ..i..... ..i..... Fast System Call
SYSEXIT SS eSP IA32_SYSENT… ... 0F 35 D19 P 0 Fast Return from Fast System Call
SYSRET SS EFlags R11 ... 0F 07 E 0 Return From Fast System Call
TEST r/m8 r8 84 r o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST r/m16/32/64 r16/32/64 85 r o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST AL imm8 A8 o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST rAX imm16/32 A9 o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST r/m8 imm8 F6 0 o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST r/m8 imm8 F6 1 U11 o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST r/m16/32/64 imm16/32 F7 0 o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST r/m16/32/64 imm16/32 F7 1 U11 o..szapc o..sz.pc .....a.. o......c Logical Compare
UCOMISD xmm xmm/m64 sse2 66 0F 2E r ....z.pc ....z.pc Unordered Compare Scalar Double-FP Values and Set EFLAGS
UCOMISS xmm xmm/m32 sse1 0F 2E r ....z.pc ....z.pc Unordered Compare Scalar Single-FP Values and Set EFLAGS
UD r r/m 0F B9 r M26 Undefined Instruction
UD2 0F 0B Undefined Instruction
UNPCKHPD xmm xmm/m128 sse2 66 0F 15 r Unpack and Interleave High Packed Double-FP Values
UNPCKHPS xmm xmm/m64 sse1 0F 15 r Unpack and Interleave High Packed Single-FP Values
UNPCKLPD xmm xmm/m128 sse2 66 0F 14 r Unpack and Interleave Low Packed Double-FP Values
UNPCKLPS xmm xmm/m64 sse1 0F 14 r Unpack and Interleave Low Packed Single-FP Values
VERR r/m16 0F 00 4 P ....z... ....z... Verify a Segment for Reading
VERW r/m16 0F 00 5 P ....z... ....z... Verify a Segment for Writing
VMCALL vmx 0F 01 C1 0 D32 P 0 o..szapc o..szapc Call to VM Monitor
VMCLEAR m64 vmx 66 0F C7 6 D32 P 0 o..szapc o..szapc Clear Virtual-Machine Control Structure
VMLAUNCH vmx 0F 01 C2 0 D32 P 0 o..szapc o..szapc Launch Virtual Machine
VMPTRLD m64 vmx 0F C7 6 D32 P 0 o..szapc o..szapc Load Pointer to Virtual-Machine Control Structure
VMPTRST m64 vmx 0F C7 7 D32 P 0 o..szapc o..szapc Store Pointer to Virtual-Machine Control Structure
VMREAD r/m64 r64 vmx 0F 78 r D32 E 0 o..szapc o..szapc Read Field from Virtual-Machine Control Structure
VMRESUME vmx 0F 01 C3 0 D32 P 0 o..szapc o..szapc Resume Virtual Machine
VMWRITE r64 r/m64 vmx 0F 79 r D32 E 0 o..szapc o..szapc Write Field to Virtual-Machine Control Structure
VMXOFF vmx 0F 01 C4 0 D32 P 0 o..szapc o..szapc Leave VMX Operation
VMXON m64 vmx F3 0F C7 6 D32 P 0 o..szapc o..szapc Enter VMX Operation
WBINVD 0F 09 0 Write Back and Invalidate Cache
WRMSR MSR rCX rAX rDX 0F 30 0 Write to Model Specific Register
XADD r/m8 r8 0F C0 r L o..szapc o..szapc Exchange and Add
XADD r/m16/32/64 r16/32/64 0F C1 r L o..szapc o..szapc Exchange and Add
XCHG r8 r/m8 86 r L Exchange Register/Memory with Register
XCHG r16/32/64 r/m16/32/64 87 r L Exchange Register/Memory with Register
XCHG r16/32/64 rAX 90+r Exchange Register/Memory with Register
XGETBV EDX EAX ECX XCR 0F 01 D0 2 C2++ Get Value of Extended Control Register
XLAT AL m8 D7 Table Look-up Translation
XLATB AL m8
XOR r/m8 r8 30 r L o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r/m16/32/64 r16/32/64 31 r L o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r8 r/m8 32 r o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r16/32/64 r/m16/32/64 33 r o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR AL imm8 34 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR rAX imm16/32 35 o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r/m8 imm8 80 6 L o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r/m16/32/64 imm16/32 81 6 L o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR r/m16/32/64 imm8 83 6 L o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XORPD xmm xmm/m128 sse2 66 0F 57 r Bitwise Logical XOR for Double-FP Values
XORPS xmm xmm/m128 sse1 0F 57 r Bitwise Logical XOR for Single-FP Values
XRSTOR ST ST1 ST2 ... 0F AE 5 C2++ E Restore Processor Extended States
XSAVE m EDX EAX ... 0F AE 4 C2++ Save Processor Extended States
XSAVE m EDX EAX ... 0F AE 4 C2++ E Save Processor Extended States
XSETBV XCR ECX EDX EAX 0F 01 D1 2 C2++ 0 Set Extended Control Register

Printing is not enabled. You can order a printed copy in the store, or get access to benefits, which include also printable HTML and PDF files.

General notes:

  1. 90 NOP
    1. 90 NOP is not really aliased to XCHG eAX, eAX instruction. This is important in 64-bit mode where the implicit zero-extension to RAX does not happen
  2. LAHF, SAHF
    1. Invalid on early steppings of EM64T architecture; that's why they need CPUID.80000001H:ECX.LAHF-SAHF[bit 0]
  3. SAL
    1. sandpile.org -- IA-32 architecture -- opcode groups
  4. FSTP1
    1. Christian Ludloff wrote: While FSTP (D9 /3, mod < 11b), FSTP8 (DF /2, mod = 11b), and FSTP9 (DF /3, mod = 11b) do signal stack underflow, FSTP1 (D9 /3, mod = 11b) does not.
  5. FNENI and FNDISI
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
  6. FNSETPM
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
  7. FFREEP
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  8. X87 aliases
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  9. INT1, ICEBP
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
  10. REP prefixes
    1. Flags aren't updated until after the last iteration to make the operation faster
  11. TEST
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
  12. CALLF, JMPF
    1. AMD64 Architecture Programmer's Manual Volume 3: If the operand-size is 32 or 64 bits, the operand is a 16-bit selector followed by a 32-bit offset. (On AMD64 architecture, 64-bit offset is not supported)
  13. SMSW r32/64
    1. Some processors support reading whole CR0 register, causing a security flaw.
  14. SYSCALL
    1. On AMD64 architecture, SYSCALL is valid also in legacy mode
  15. 0F0D NOP
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
  16. Hintable NOP
    1. See U.S. Patent 5,701,442
    2. sandpile.org -- IA-32 architecture -- opcode groups
  17. MOV from/to CRn, DRn, TRn
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
  18. SYSENTER
    1. On AMD64 architecture, SYSENTER is valid only in legacy mode.
  19. SYSEXIT
    1. On AMD64 architecture, SYSEXIT is not valid in long mode.
  20. GETSEC Leaf Functions
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z: The GETSEC instruction supports multiple leaf functions. Leaf functions are selected by the value in EAX at the time GETSEC is executed. The following leaf functions are available: CAPABILITIES, ENTERACCS, EXITAC, SENTER, SEXIT, PARAMETERS, SMCTRL, WAKEUP. GETSEC instruction operands are specific to selected leaf function.
  21. MOVQ
    1. On AMD64 architecture, only MOVD mnemonic is used.
  22. CMOVcc
    1. The destination register operand is zero-extended to 64 bits even if the condition is not satisfied.
  23. SETcc
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
  24. CMPXCHG with memory operand
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: CMPXCHG always does a read-modify-write on the memory operand.
  25. LFS, LGS, LSS
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: Executing LFS, LGS, or LSS with a 64-bit operand size only loads a 32-bit general purpose register and the specified segment register. (On AMD64 architecture, 64-bit offset is not supported)
  26. 0FB9 UD
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes
  27. BSF, BSR
    1. On AMD64 architecture, BSF and BSR instructions act differently if the content of the source operand is 0
  28. CMPXCHG8B, CMPXCHG16B
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The CMPXCHG8B and CMPXCHG16B instructions always do a read-modify-write on the memory operand.
    3. CMPXCHG16B is invalid on early steppings of AMD64 architecture.
  29. BSWAP r16
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: When the BSWAP instruction references a 16-bit register, the result is undefined.
    2. AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions: The result of applying the BSWAP instruction to a 16-bit register is undefined.
  30. MASKMOVQ
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction causes a transition from x87 FPU to MMX technology state.
  31. Short and near jumps
    1. Use of operand-size prefix in 64-bit mode may result in implementation-dependent behaviour; on AMD64 architecture, this prefix acts as expected
  32. Intel VMX
    1. Intel VMX is not binary-compatible with AMD SVM
  33. Intel SSE4
    1. AMD64 architecture does not support SSE4 instructions but PTEST as part of SSE5

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

Create a hypertext reference to this edition's mnemonic group (append mnemonic's starting letter at the end of the following line):

http://ref.x86asm.net/coder64-abc.html#

32/64-bit ModR/M Byte

REX.R=1
r8(/r) without REX prefix AL CL DL BL AH CH DH BH
r8(/r) with any REX prefix AL CL DL BL SPL BPL SIL DIL R8B R9B R10B R11B R12B R13B R14B R15B
r16(/r) AX CX DX BX SP BP SI DI R8W R9W R10W R11W R12W R13W R14W R15W
r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI R8D R9D R10D R11D R12D R13D R14D R15D
r64(/r) RAX RCX RDX RBX RSP RBP RSI RDI R8 R9 R10 R11 R12 R13 R14 R15
mm(/r) MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7
xmm(/r) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15
sreg ES CS SS DS FS GS res. res. ES CS SS DS FS GS res. res.
eee CR0 invd CR2 CR3 CR4 invd invd invd CR8 invd invd invd invd invd invd invd
eee DR0 DR1 DR2 DR3 DR41 DR51 DR6 DR7 invd invd invd invd invd invd invd invd
(In decimal) /digit (Opcode) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
(In binary) REG = 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Effective Address Effective Address REX.B=1 Mod R/M Value of ModR/M Byte (in Hex) Value of ModR/M Byte (in Hex)
[RAX/EAX] [R8/R8D] 00 000 00 08 10 18 20 28 30 38 00 08 10 18 20 28 30 38
[RCX/ECX] [R9/R9D] 001 01 09 11 19 21 29 31 39 01 09 11 19 21 29 31 39
[RDX/EDX] [R10/R10D] 010 02 0A 12 1A 22 2A 32 3A 02 0A 12 1A 22 2A 32 3A
[RBX/EBX] [R11/R11D] 011 03 0B 13 1B 23 2B 33 3B 03 0B 13 1B 23 2B 33 3B
[sib] [sib] 100 04 0C 14 1C 24 2C 34 3C 04 0C 14 1C 24 2C 34 3C
[RIP/EIP]+disp32 [RIP/EIP]+disp32 101 05 0D 15 1D 25 2D 35 3D 05 0D 15 1D 25 2D 35 3D
[RSI/ESI] [R14/R14D] 110 06 0E 16 1E 26 2E 36 3E 06 0E 16 1E 26 2E 36 3E
[RDI/EDI] [R15/R15D] 111 07 0F 17 1F 27 2F 37 3F 0F 07 17 1F 27 2F 37 3F
[RAX/EAX]+disp8 [R8/R8D]+disp8 01 000 40 48 50 58 60 68 70 78 40 48 50 58 60 68 70 78
[RCX/EDX]+disp8 [R9/R9D]+disp8 001 41 49 51 59 61 69 71 79 41 49 51 59 61 69 71 79
[RDX/EDX]+disp8 [R10/R10D]+disp8 010 42 4A 52 5A 62 6A 72 7A 42 4A 52 5A 62 6A 72 7A
[RBX/EBX]+disp8 [R11/R11D]+disp8 011 43 4B 53 5B 63 6B 73 7B 43 4B 53 5B 63 6B 73 7B
[sib]+disp8 [sib]+disp8 100 44 4C 54 5C 64 6C 74 7C 44 4C 54 5C 64 6C 74 7C
[RBP/EBP]+disp8 [R13/R13D]+disp8 101 45 4D 55 5D 65 6D 75 7D 45 4D 55 5D 65 6D 75 7D
[RSI/ESI]+disp8 [R14/R14D]+disp8 110 46 4E 56 5E 66 6E 76 7E 46 4E 56 5E 66 6E 76 7E
[RDI/EDI]+disp8 [R15/R15D]+disp8 111 47 4F 57 5F 67 6F 77 7F 47 4F 57 5F 67 6F 77 7F
[RAX/EAX]+disp32 [R8/R8D]+disp32 10 000 80 88 90 98 A0 A8 B0 B8 80 88 90 98 A0 A8 B0 B8
[RCX/ECX]+disp32 [R9/R9D]+disp32 001 81 89 91 99 A1 A9 B1 B9 81 89 91 99 A1 A9 B1 B9
[RDX/EDX]+disp32 [R10/R10D]+disp32 010 82 8A 92 9A A2 AA B2 BA 82 8A 92 9A A2 AA B2 BA
[RBX/EBX]+disp32 [R11/R11D]+disp32 011 83 8B 93 9B A3 AB B3 BB 83 8B 93 9B A3 AB B3 BB
[sib]+disp32 [sib]+disp32 100 84 8C 94 9C A4 AC B4 BC 84 8C 94 9C A4 AC B4 BC
[RBP/EBP]+disp32 [R13/R13D]+disp32 101 85 8D 95 9D A5 AD B5 BD 85 8D 95 9D A5 AD B5 BD
[RSI/ESI]+disp32 [R14/R14D]+disp32 110 86 8E 96 9E A6 AE B6 BE 86 8E 96 9E A6 AE B6 BE
[RDI/EDI]+disp32 [R15/R15D]+disp32 111 87 8F 97 9F A7 AF B7 BF 87 8F 97 9F A7 AF B7 BF
AL/AX/EAX/RAX/ST0/MM0/XMM0 R8B/R8W/R8D/R8/ST0/MM0/XMM8 11 000 C0 C8 D0 D8 E0 E8 F0 F8 C0 C8 D0 D8 E0 E8 F0 F8
CL/CX/ECX/RCX/ST1/MM1/XMM1 R9B/R9W/R9D/R9/ST1/MM1/XMM9 001 C1 C9 D1 D9 E1 E9 F1 F9 C1 C9 D1 D9 E1 E9 F1 F9
DL/DX/EDX/RDX/ST2/MM2/XMM2 R10B/R10W/R10D/R10/ST2/MM2/XMM10 010 C2 CA D2 DA E2 EA F2 FA C2 CA D2 DA E2 EA F2 FA
BL/BX/EBX/RBX/ST3/MM3/XMM3 R11B/R11W/R11D/R11/ST3/MM3/XMM11 011 C3 CB D3 DB E3 EB F3 FB C3 CB D3 DB E3 EB F3 FB
AH/SP/ESP/RSP/ST4/MM4/XMM4 R12B/R12W/R12D/R12/ST4/MM4/XMM12 100 C4 CC D4 DC E4 EC F4 FC C4 CC D4 DC E4 EC F4 FC
CH/BP/EBP/RBP/ST5/MM5/XMM5 R13B/R13W/R13D/R13/ST5/MM5/XMM13 101 C5 CD D5 DD E5 ED F5 FD C5 CD D5 DD E5 ED F5 FD
DH/SI/ESI/RSI/ST6/MM6/XMM6 R14B/R14W/R14D/R14/ST6/MM6/XMM14 110 C6 CE D6 DE E6 EE F6 FE C6 CE D6 DE E6 EE F6 FE
BH/DI/EDI/RDI/ST7/MM7/XMM7 R15B/R15W/R15D/R15/ST7/MM7/XMM15 111 C7 CF D7 DF E7 EF F7 FF C7 CF D7 DF E7 EF F7 FF

32/64-bit SIB Byte

REX.B=1
r64 RAX RCX RDX RBX RSP →1 RSI RDI R8 R9 R10 R11 R12 →2 R14 R15
r32 EAX ECX EDX EBX ESP →1 ESI EDI R8D R9D R10D R11D R12D →2 R14D R15D
(In decimal) Base = 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
(In binary) Base = 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Scaled Index Scaled Index
REX.X=1		 SS Index Value of SIB Byte (in Hex) Value of SIB Byte (in Hex)
[RAX/EAX] [R8/R8D] 00 000 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07
[RCX/ECX] [R9/R9D] 001 08 09 0A 0B 0C 0D 0E 0F 08 09 0A 0B 0C 0D 0E 0F
[RDX/EDX] [R10/R10D] 010 10 11 12 13 14 15 16 17 10 11 12 13 14 15 16 17
[RBX/EBX] [R11/R11D] 011 18 19 1A 1B 1C 1D 1E 1F 18 19 1A 1B 1C 1D 1E 1F
none [R12/R12D] 100 20 21 22 23 24 25 26 27 20 21 22 23 24 25 26 27
[RBP/EBP] [R13/R13D] 101 28 29 2A 2B 2C 2D 2E 2F 28 29 2A 2B 2C 2D 2E 2F
[RSI/ESI] [R14/R14D] 110 30 31 32 33 34 35 36 37 30 31 32 33 34 35 36 37
[RDI/EDI] [R15/R15D] 111 38 39 3A 3B 3C 3D 3E 3F 38 39 3A 3B 3C 3D 3E 3F
[RAX/EAX*2] [R8/R8D*2] 01 000 40 41 42 43 44 45 46 47 40 41 42 43 44 45 46 47
[RCX/ECX*2] [R9/R9D*2] 001 48 49 4A 4B 4C 4D 4E 4F 48 49 4A 4B 4C 4D 4E 4F
[RDX/EDX*2] [R10/R10D*2] 010 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57
[RBX/EBX*2] [R11/R11D*2] 011 58 59 5A 5B 5C 5D 5E 5F 58 59 5A 5B 5C 5D 5E 5F
none [R12/R12D*2] 100 60 61 62 63 64 65 66 67 60 61 62 63 64 65 66 67
[RBP/EBP*2] [R13/R13*2] 101 68 69 6A 6B 6C 6D 6E 6F 68 69 6A 6B 6C 6D 6E 6F
[RSI/ESI*2] [R14/R14D*2] 110 70 71 72 73 74 75 76 77 70 71 72 73 74 75 76 77
[RDI/EDI*2] [R15/R15D*2] 111 78 79 7A 7B 7C 7D 7E 7F 78 79 7A 7B 7C 7D 7E 7F
[RAX/EAX*4] [R8/R8D*4] 10 000 80 81 82 83 84 85 86 87 80 81 82 83 84 85 86 87
[RCX/ECX*4] [R9/R9D*4] 001 88 89 8A 8B 8C 8D 8E 8F 88 89 8A 8B 8C 8D 8E 8F
[RDX/EDX*4] [R10/R10D*4] 010 90 91 92 93 94 95 96 97 90 91 92 93 94 95 96 97
[RBX/EBX*4] [R11/E11D*4] 011 98 99 9A 9B 9C 9D 9E 9F 98 99 9A 9B 9C 9D 9E 9F
none [R12/R12D*4] 100 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7
[RBP/EBP*4] [R13/R13D*4] 101 A8 A9 AA AB AC AD AE AF A8 A9 AA AB AC AD AE AF
[RSI/ESI*4] [R14/R14D*4] 110 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
[RDI/EDI*4] [R15/R15D*4] 111 B8 B9 BA BB BC BD BE BF B8 B9 BA BB BC BD BE BF
[RAX/EAX*8] [R8/R8D*8] 11 000 C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7
[RCX/ECX*8] [R9/R9D*8] 001 C8 C9 CA CB CC CD CE CF C8 C9 CA CB CC CD CE CF
[RDX/EDX*8] [R10/R10D*8] 010 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
[RBX/EBX*8] [R11/R11D*8] 011 D8 D9 DA DB DC DD DE DF D8 D9 DA DB DC DD DE DF
none [R12/R12D*8] 100 E0 E1 E2 E3 E4 E5 E6 E7 E0 E1 E2 E3 E4 E5 E6 E7
[RBP/EBP*8] [R13/R13D*8] 101 E8 E9 EA EB EC ED EE EF E8 E9 EA EB EC ED EE EF
[RSI/ESI*8] [R14/R14D*8] 110 F0 F1 F2 F3 F4 F5 F6 F7 F0 F1 F2 F3 F4 F5 F6 F7
[RDI/EDI*8] [R15/R15D*8] 111 F8 F9 FA FB FC FD FE FF F8 F9 FA FB FC FD FE FF
SIB Note 1
Mod bits base
00 disp32
01 RBP/EBP+disp8
10 RBP/EBP+disp32
SIB Note 2
Mod bits base
00 disp32
01 R13/R13D+disp8
10 R13/R13D+disp32

16-bit ModR/M Byte

r8(/r) AL CL DL BL AH CH DH BH
r16(/r) AX CX DX BX SP BP SI DI
r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI
mm(/r) MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7
xmm(/r) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
sreg ES CS SS DS FS GS res. res.
eee CR0 invd CR2 CR3 CR4 invd invd invd
eee DR0 DR1 DR2 DR3 DR41 DR51 DR6 DR7
(In decimal) /digit (Opcode) 0 1 2 3 4 5 6 7
(In binary) REG = 000 001 010 011 100 101 110 111
Effective Address Mod R/M Value of ModR/M Byte (in Hex)
[BX+SI] 00 000 00 08 10 18 20 28 30 38
[BX+DI] 001 01 09 11 19 21 29 31 39
[BP+SI] 010 02 0A 12 1A 22 2A 32 3A
[BP+DI] 011 03 0B 13 1B 23 2B 33 3B
[SI] 100 04 0C 14 1C 24 2C 34 3C
[DI] 101 05 0D 15 1D 25 2D 35 3D
disp16 110 06 0E 16 1E 26 2E 36 3E
[BX] 111 07 0F 17 1F 27 2F 37 3F
[BX+SI]+disp8 01 000 40 48 50 58 60 68 70 78
[BX+DI]+disp8 001 41 49 51 59 61 69 71 79
[BP+SI]+disp8 010 42 4A 52 5A 62 6A 72 7A
[BP+DI]+disp8 011 43 4B 53 5B 63 6B 73 7B
[SI]+disp8 100 44 4C 54 5C 64 6C 74 7C
[DI]+disp8 101 45 4D 55 5D 65 6D 75 7D
[BP]+disp8 110 46 4E 56 5E 66 6E 76 7E
[BX]+disp8 111 47 4F 57 5F 67 6F 77 7F
[BX+SI]+disp16 10 000 80 88 90 98 A0 A8 B0 B8
[BX+DI]+disp16 001 81 89 91 99 A1 A9 B1 B9
[BP+SI]+disp16 010 82 8A 92 9A A2 AA B2 BA
[BP+DI]+disp16 011 83 8B 93 9B A3 AB B3 BB
[SI]+disp16 100 84 8C 94 9C A4 AC B4 BC
[DI]+disp16 101 85 8D 95 9D A5 AD B5 BD
[BP]+disp16 110 86 8E 96 9E A6 AE B6 BE
[BX]+disp16 111 87 8F 97 9F A7 AF B7 BF
AL/AX/EAX/ST0/MM0/XMM0 11 000 C0 C8 D0 D8 E0 E8 F0 F8
CL/CX/ECX/ST1/MM1/XMM1 001 C1 C9 D1 D9 E1 E9 F1 F9
DL/DX/EDX/ST2/MM2/XMM2 010 C2 CA D2 DA E2 EA F2 FA
BL/BX/EBX/ST3/MM3/XMM3 011 C3 CB D3 DB E3 EB F3 FB
AH/SP/ESP/ST4/MM4/XMM4 100 C4 CC D4 DC E4 EC F4 FC
CH/BP/EBP/ST5/MM5/XMM5 101 C5 CD D5 DD E5 ED F5 FD
DH/SI/ESI/ST6/MM6/XMM6 110 C6 CE D6 DE E6 EE F6 FE
BH/DI/EDI/ST7/MM7/XMM7 111 C7 CF D7 DF E7 EF F7 FF
ModR/M Note 1: Debug Registers DR4 and DR5
References to debug registers DR4 and DR5 cause an undefined opcode (#UD) exception to be generated when CR4.DE[bit 3] (Debugging Extensions) set; when clear, processor aliases references to registers DR4 and DR5 to DR6 and DR7 for compatibility with software written to run on earlier IA-32 processors.

Your Notes: