X86 Opcode and Instruction Reference Home

Other editions: coder32-abc, coder64-abc, coder-abc, geek64-abc, geek-abc
32-bit ModR/M Byte | 32-bit SIB Byte
16-bit ModR/M Byte

alphabetic index:

 A    B    C    D    E    F    G    H    I    J    L    M    N    O    P    R    S    T    U    V    W    X  
mnemonic op1 op2 op3 op4 iext pf 0F po so flds o proc st m rl x grp1 grp2 grp3 tested f modif f def f undef f f values description, notes                                        
AAA AL AH 37 gen arith decimal .....a.. o..szapc .....a.c o..sz.p. ASCII Adjust After Addition
AAD AL AH D5 0A gen arith decimal o..szapc ...sz.p. o....a.c ASCII Adjust AX Before Division
AAM AL AH D4 0A gen arith decimal o..szapc ...sz.p. o....a.c ASCII Adjust AX After Multiply
AAS AL AH 3F gen arith decimal .....a.. o..szapc .....a.c o..sz.p. ASCII Adjust AL After Subtraction
ADC Eb Gb 10 dw r L gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Ev Gv 11 dW r L gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Gb Eb 12 Dw r gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Gv Ev 13 DW r gen arith binary .......c o..szapc o..szapc Add with Carry
ADC AL Ib 14 w gen arith binary .......c o..szapc o..szapc Add with Carry
ADC eAX Iv 15 W gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Eb Ib 80 w 2 L gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Ev Iv 81 W 2 L gen arith binary .......c o..szapc o..szapc Add with Carry
ADC alias Eb Ib 82 w 2 L gen arith binary .......c o..szapc o..szapc Add with Carry
ADC Ev Ibs 83 SW 2 L gen arith binary .......c o..szapc o..szapc Add with Carry
ADD Eb Gb 00 dw r L gen arith binary o..szapc o..szapc Add
ADD Ev Gv 01 dW r L gen arith binary o..szapc o..szapc Add
ADD Gb Eb 02 Dw r gen arith binary o..szapc o..szapc Add
ADD Gv Ev 03 DW r gen arith binary o..szapc o..szapc Add
ADD AL Ib 04 w gen arith binary o..szapc o..szapc Add
ADD eAX Iv 05 W gen arith binary o..szapc o..szapc Add
ADD Eb Ib 80 w 0 L gen arith binary o..szapc o..szapc Add
ADD Ev Iv 81 W 0 L gen arith binary o..szapc o..szapc Add
ADD alias Eb Ib 82 w 0 L gen arith binary o..szapc o..szapc Add
ADD Ev Ibs 83 SW 0 L gen arith binary o..szapc o..szapc Add
ADDPD Vpd Wpd sse2 66 0F 58 r P4+ pcksclr arith Add Packed Double-FP Values
ADDPS Vps Wps sse1 0F 58 r P3+ simdfp arith Add Packed Single-FP Values
ADDSD Vsd Wsd sse2 F2 0F 58 r P4+ pcksclr arith Add Scalar Double-FP Values
ADDSS Vss Wss sse1 F3 0F 58 r P3+ simdfp arith Add Scalar Single-FP Values
ADDSUBPD Vpd Wpd sse3 66 0F D0 r P4++ simdfp arith Packed Double-FP Add/Subtract
ADDSUBPS Vps Wps sse3 F2 0F D0 r P4++ simdfp arith Packed Single-FP Add/Subtract
ADX AL AH Ib D5 gen arith decimal o..szapc ...sz.p. o....a.c Adjust AX Before Division
ALTER 64 P4 U2 prefix branch cond Alternating branch prefix (only with Jcc instructions)
AMX AL AH Ib D4 gen arith decimal o..szapc ...sz.p. o....a.c Adjust AX After Multiply
AND Eb Gb 20 dw r L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Ev Gv 21 dW r L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Gb Eb 22 Dw r gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Gv Ev 23 DW r gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND AL Ib 24 w gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND eAX Iv 25 W gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Eb Ib 80 w 4 L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Ev Iv 81 W 4 L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND alias Eb Ib 82 w 4 L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
AND Ev Ibs 83 SW 4 03+ L gen logical o..szapc o..sz.pc .....a.. o......c Logical AND
ANDNPD Vpd Wpd sse2 66 0F 55 r P4+ pcksclr logical Bitwise Logical AND NOT of Packed Double-FP Values
ANDNPS Vps Wps sse1 0F 55 r P3+ simdfp logical Bitwise Logical AND NOT of Packed Single-FP Values
ANDPD Vpd Wpd sse2 66 0F 54 r P4+ pcksclr logical Bitwise Logical AND of Packed Double-FP Values
ANDPS Vps Wps sse1 0F 54 r P3+ simdfp logical Bitwise Logical AND of Packed Single-FP Values
ARPL Ew Gw 63 r 02+ system ....z... ....z... Adjust RPL Field of Segment Selector
BLENDPD Vpd Wpd Ib sse41 66 0F 3A 0D r C2++ D32 simdfp datamov Blend Packed Double-FP Values
BLENDPS Vps Wps Ib sse41 66 0F 3A 0C r C2++ D32 simdfp datamov Blend Packed Single-FP Values
BLENDVPD Vpd Wpd XMM0 sse41 66 0F 38 15 r C2++ D32 simdint datamov Variable Blend Packed Double-FP Values
BLENDVPS Vps Wps XMM0 sse41 66 0F 38 14 r C2++ D32 simdint datamov Variable Blend Packed Single-FP Values
BOUND Gv Ma Fv 62 D r 01+ f gen break stack ..i..... ..i..... ..i..... Check Array Index Against Bounds
BSF Gv Ev 0F BC r 03+ gen bit o..szapc ....z... o..s.apc Bit Scan Forward
BSR Gv Ev 0F BD r 03+ gen bit o..szapc ....z... o..s.apc Bit Scan Reverse
BSWAP Zv 0F C8 +r 04+ D29 gen datamov Byte Swap
BT Ev Gv 0F A3 r 03+ gen bit o..szapc .......c o..szap. Bit Test
BT Ev Ib 0F BA 4 03+ gen bit o..szapc .......c o..szap. Bit Test
BTC Ev Ib 0F BA 7 03+ L gen bit o..szapc .......c o..szap. Bit Test and Complement
BTC Ev Gv 0F BB r 03+ L gen bit o..szapc .......c o..szap. Bit Test and Complement
BTR Ev Gv 0F B3 r 03+ L gen bit o..szapc .......c o..szap. Bit Test and Reset
BTR Ev Ib 0F BA 6 03+ L gen bit o..szapc .......c o..szap. Bit Test and Reset
BTS Ev Gv 0F AB r 03+ L gen bit o..szapc .......c o..szap. Bit Test and Set
BTS Ev Ib 0F BA 5 03+ L gen bit o..szapc .......c o..szap. Bit Test and Set
CALL Jv E8 gen branch stack Call Procedure
CALL Ev FF 2 gen branch stack Call Procedure
CALLF Ap 9A gen branch stack Call Procedure
CALLF Mp FF 3 gen branch stack Call Procedure
CBW AX AL 98 gen conver Convert Byte to Word
CDQ EDX EAX 99 03+ gen conver Convert Doubleword to Quadword
CLC F8 gen flgctrl .......c .......c .......c Clear Carry Flag
CLD FC gen flgctrl .d...... .d...... .d...... Clear Direction Flag
CLFLUSH Mb sse2 0F AE 7 P4+ cachect Flush Cache Line
CLI FA f1 gen flgctrl ..i..... ..i..... ..i..... Clear Interrupt Flag
CLTS CR0 0F 06 02+ 0 system Clear Task-Switched Flag in CR0
CMC F5 gen flgctrl .......c .......c .......c Complement Carry Flag
CMOVB Gv Ev 0F 42 ttTn r PP+ gen datamov .......c Conditional Move - below/not above or equal/carry (CF=1)
CMOVNAE Gv Ev
CMOVC Gv Ev
CMOVBE Gv Ev 0F 46 tTTn r PP+ gen datamov ....z..c Conditional Move - below or equal/not above (CF=1 OR ZF=1)
CMOVNA Gv Ev
CMOVL Gv Ev 0F 4C TTtn r PP+ gen datamov o..s.... Conditional Move - less/not greater (SF!=OF)
CMOVNGE Gv Ev
CMOVLE Gv Ev 0F 4E TTTn r PP+ gen datamov o..sz... Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
CMOVNG Gv Ev
CMOVNB Gv Ev 0F 43 ttTN r PP+ gen datamov .......c Conditional Move - not below/above or equal/not carry (CF=0)
CMOVAE Gv Ev
CMOVNC Gv Ev
CMOVNBE Gv Ev 0F 47 tTTN r PP+ gen datamov ....z..c Conditional Move - not below or equal/above (CF=0 AND ZF=0)
CMOVA Gv Ev
CMOVNL Gv Ev 0F 4D TTtN r PP+ gen datamov o..s.... Conditional Move - not less/greater or equal (SF=OF)
CMOVGE Gv Ev
CMOVNLE Gv Ev 0F 4F TTTN r PP+ gen datamov o..sz... Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
CMOVG Gv Ev
CMOVNO Gv Ev 0F 41 tttN r PP+ gen datamov o....... Conditional Move - not overflow (OF=0)
CMOVNP Gv Ev 0F 4B TtTN r PP+ gen datamov ......p. Conditional Move - not parity/parity odd (PF=0)
CMOVPO Gv Ev
CMOVNS Gv Ev 0F 49 TttN r PP+ gen datamov ...s.... Conditional Move - not sign (SF=0)
CMOVNZ Gv Ev 0F 45 tTtN r PP+ gen datamov ....z... Conditional Move - not zero/not equal (ZF=0)
CMOVNE Gv Ev
CMOVO Gv Ev 0F 40 tttn r PP+ gen datamov o....... Conditional Move - overflow (OF=1)
CMOVP Gv Ev 0F 4A TtTn r PP+ gen datamov ......p. Conditional Move - parity/parity even (PF=1)
CMOVPE Gv Ev
CMOVS Gv Ev 0F 48 Tttn r PP+ gen datamov ...s.... Conditional Move - sign (SF=1)
CMOVZ Gv Ev 0F 44 tTtn r PP+ gen datamov ....z... Conditional Move - zero/equal (ZF=1)
CMOVE Gv Ev
CMP Eb Gb 38 dw r gen arith binary o..szapc o..szapc Compare Two Operands
CMP Ev Gv 39 dW r gen arith binary o..szapc o..szapc Compare Two Operands
CMP Gb Eb 3A Dw r gen arith binary o..szapc o..szapc Compare Two Operands
CMP Gv Ev 3B DW r gen arith binary o..szapc o..szapc Compare Two Operands
CMP AL Ib 3C w gen arith binary o..szapc o..szapc Compare Two Operands
CMP eAX Iv 3D W gen arith binary o..szapc o..szapc Compare Two Operands
CMP Eb Ib 80 w 7 gen arith binary o..szapc o..szapc Compare Two Operands
CMP Ev Iv 81 W 7 gen arith binary o..szapc o..szapc Compare Two Operands
CMP alias Eb Ib 82 w 7 gen arith binary o..szapc o..szapc Compare Two Operands
CMP Ev Ibs 83 SW 7 gen arith binary o..szapc o..szapc Compare Two Operands
CMPPD Vpd Wpd Ib sse2 66 0F C2 r P4+ pcksclr compar Compare Packed Double-FP Values
CMPPS Vps Wps Ib sse1 0F C2 r P3+ simdfp compar Compare Packed Single-FP Values
CMPS Yb Xb A6 w gen arith string binary .d...... o..szapc o..szapc Compare String Operands
CMPSB Yb Xb
CMPS Ywo Xwo A7 W gen arith string binary .d...... o..szapc o..szapc Compare String Operands
CMPSW Ywo Xwo
CMPS Yv Xv A7 W 03+ gen arith string binary .d...... o..szapc o..szapc Compare String Operands
CMPSD Ydo Xdo
CMPSD Vsd Wsd Ib sse2 F2 0F C2 r P4+ pcksclr compar Compare Scalar Double-FP Values
CMPSS Vss Wss Ib sse1 F3 0F C2 r P3+ simdfp compar Compare Scalar Single-FP Values
CMPXCHG Eb AL Gb 0F B0 dw r 04+ D26 L gen datamov arith binary o..szapc o..szapc Compare and Exchange
CMPXCHG Ev eAX Gv 0F B1 dW r 04+ D26 L gen datamov arith binary o..szapc o..szapc Compare and Exchange
CMPXCHG8B Mq EAX EDX ... 0F C7 1 P1+ D28 L gen datamov arith binary ....z... ....z... Compare and Exchange Bytes
COMISD Vsd Wsd sse2 66 0F 2F r P4+ pcksclr compar ....z.pc ....z.pc Compare Scalar Ordered Double-FP Values and Set EFLAGS
COMISS Vss Wss sse1 0F 2F r P3+ simdfp compar ....z.pc ....z.pc Compare Scalar Ordered Single-FP Values and Set EFLAGS
CPUID I... EAX ECX ... 0F A2 04++ gen control CPU Identification
CRC32 Gd Eb sse42 F2 0F 38 F0 r C2++ D32 Accumulate CRC32 Value
CRC32 Gd Ev sse42 F2 0F 38 F1 r C2++ D32 Accumulate CRC32 Value
CS CS 2E prefix segreg CS segment override prefix
CVTDQ2PD Vpd Wdq sse2 F3 0F E6 r P4+ pcksclr conver Convert Packed DW Integers to Double-FP Values
CVTDQ2PS Vps Wdq sse2 0F 5B r P4+ pcksp Convert Packed DW Integers to Single-FP Values
CVTPD2DQ Vdq Wpd sse2 F2 0F E6 r P4+ pcksclr conver Convert Packed Double-FP Values to DW Integers
CVTPD2PI Ppi Wpd sse2 66 0F 2D r P4+ pcksclr conver Convert Packed Double-FP Values to DW Integers
CVTPD2PS Vps Wpd sse2 66 0F 5A r P4+ pcksclr conver Convert Packed Double-FP Values to Single-FP Values
CVTPI2PD Vpd Qpi sse2 66 0F 2A r P4+ pcksclr conver Convert Packed DW Integers to Double-FP Values
CVTPI2PS Vps Qpi sse1 0F 2A r P3+ conver Convert Packed DW Integers to Single-FP Values
CVTPS2DQ Vdq Wps sse2 66 0F 5B r P4+ pcksp Convert Packed Single-FP Values to DW Integers
CVTPS2PD Vpd Wps sse2 0F 5A r P4+ pcksclr conver Convert Packed Single-FP Values to Double-FP Values
CVTPS2PI Ppi Wpsq sse1 0F 2D r P3+ conver Convert Packed Single-FP Values to DW Integers
CVTSD2SI Gd Wsd sse2 F2 0F 2D r P4+ pcksclr conver Convert Scalar Double-FP Value to DW Integer
CVTSD2SS Vss Wsd sse2 F2 0F 5A r P4+ pcksclr conver Convert Scalar Double-FP Value to Scalar Single-FP Value
CVTSI2SD Vsd Ed sse2 F2 0F 2A r P4+ pcksclr conver Convert DW Integer to Scalar Double-FP Value
CVTSI2SS Vss Ed sse1 F3 0F 2A r P3+ conver Convert DW Integer to Scalar Single-FP Value
CVTSS2SD Vsd Wss sse2 F3 0F 5A r P4+ pcksclr conver Convert Scalar Single-FP Value to Scalar Double-FP Value
CVTSS2SI Gd Wss sse1 F3 0F 2D r P3+ conver Convert Scalar Single-FP Value to DW Integer
CVTTPD2DQ Vdq Wpd sse2 66 0F E6 r P4+ pcksclr conver Convert with Trunc. Packed Double-FP Values to DW Integers
CVTTPD2PI Ppi Wpd sse2 66 0F 2C r P4+ pcksclr conver Convert with Trunc. Packed Double-FP Values to DW Integers
CVTTPS2DQ Vdq Wps sse2 F3 0F 5B r P4+ pcksp Convert with Trunc. Packed Single-FP Values to DW Integers
CVTTPS2PI Ppi Wpsq sse1 0F 2C r P3+ conver Convert with Trunc. Packed Single-FP Values to DW Integers
CVTTSD2SI Gd Wsd sse2 F2 0F 2C r P4+ pcksclr conver Conv. with Trunc. Scalar Double-FP Value to Signed DW Int
CVTTSS2SI Gd Wss sse1 F3 0F 2C r P3+ conver Convert with Trunc. Scalar Single-FP Value to DW Integer
CWD DX AX 99 gen conver Convert Word to Doubleword
CWDE EAX AX 98 03+ gen conver Convert Word to Doubleword
DAA AL 27 gen arith decimal .....a.c o..szapc ...szapc o....... Decimal Adjust AL after Addition
DAS AL 2F gen arith decimal .....a.c o..szapc ...szapc o....... Decimal Adjust AL after Subtraction
DEC Zv 48 +r gen arith binary o..szap. o..szap. Decrement by 1
DEC Eb FE w 1 L gen arith binary o..szap. o..szap. Decrement by 1
DEC Ev FF W 1 L gen arith binary o..szap. o..szap. Decrement by 1
DIV AL AH AX Eb F6 w 6 gen arith binary o..szapc o..szapc Unsigned Divide
DIV eDX eAX Ev F7 W 6 gen arith binary o..szapc o..szapc Unsigned Divide
DIVPD Vpd Wpd sse2 66 0F 5E r P4+ pcksclr arith Divide Packed Double-FP Values
DIVPS Vps Wps sse1 0F 5E r P3+ simdfp arith Divide Packed Single-FP Values
DIVSD Vsd Wsd sse2 F2 0F 5E r P4+ pcksclr arith Divide Scalar Double-FP Values
DIVSS Vss Wss sse1 F3 0F 5E r P3+ simdfp arith Divide Scalar Single-FP Values
DPPD Vpd Wpd sse41 66 0F 3A 41 r C2++ D32 simdfp arith Dot Product of Packed Double-FP Values
DPPS Vps Wps sse41 66 0F 3A 40 r C2++ D32 simdfp arith Dot Product of Packed Single-FP Values
DS DS 3E prefix segreg DS segment override prefix
EMMS mmx 0F 77 PX+ x87fpu control Empty MMX Technology State
ENTER eBP Iw Ib C8 01+ gen stack Make Stack Frame for Procedure Parameters
ES ES 26 prefix segreg ES segment override prefix
EXTRACTPS Ed Vdq Ib sse41 66 0F 3A 17 r C2++ D32 simdfp datamov Extract Packed Single-FP Value
F2XM1 ST D9 F0 6 x87fpu trans 0123 .1.. 0.23 Compute 2x-1
FABS ST D9 E1 4 x87fpu arith 0123 .1.. 0.23 Absolute Value
FADD ST Msr D8 mf 0 x87fpu arith 0123 .1.. 0.23 Add
FADD ST EST
FADD ST Mdr DC Mf 0 x87fpu arith 0123 .1.. 0.23 Add
FADD EST ST DC 0 x87fpu arith 0123 .1.. 0.23 Add
FADDP EST ST DE 0 p x87fpu arith 0123 .1.. 0.23 Add and Pop
FADDP ST1 ST DE C1 0 p x87fpu arith 0123 .1.. 0.23 Add and Pop
FBLD ST Mbcd DF 4 s x87fpu datamov 0123 .1.. 0.23 Load Binary Coded Decimal
FBSTP Mbcd ST DF 6 p x87fpu datamov 0123 .1.. 0.23 Store BCD Integer and Pop
FCHS ST D9 E0 4 x87fpu arith 0123 .1.. 0.23 Change Sign
FCLEX 9B DB E2 4 x87fpu control 0123 0123 Clear Exceptions
FCMOVB ST EST DA 0 PP+ x87fpu datamov .......c 0123 .1.. 0.23 FP Conditional Move - below (CF=1)
FCMOVBE ST EST DA 2 PP+ x87fpu datamov ....z... 0123 .1.. 0.23 FP Conditional Move - below or equal (CF=1 or ZF=1)
FCMOVE ST EST DA 1 PP+ x87fpu datamov ....z... 0123 .1.. 0.23 FP Conditional Move - equal (ZF=1)
FCMOVNB ST EST DB 0 PP+ x87fpu datamov .......c 0123 .1.. 0.23 FP Conditional Move - not below (CF=0)
FCMOVNBE ST EST DB 2 PP+ x87fpu datamov ....z... 0123 .1.. 0.23 FP Conditional Move - below or equal (CF=0 and ZF=0)
FCMOVNE ST EST DB 1 PP+ x87fpu datamov ....z... 0123 .1.. 0.23 FP Conditional Move - not equal (ZF=0)
FCMOVNU ST EST DB 3 PP+ x87fpu datamov ......p. 0123 .1.. 0.23 FP Conditional Move - not unordered (PF=0)
FCMOVU ST EST DA 3 PP+ x87fpu datamov ......p. 0123 .1.. 0.23 FP Conditional Move - unordered (PF=1)
FCOM ST ESsr D8 mf 2 x87fpu compar 0123 0123 Compare Real
FCOM ST ST1 D8 D1 2 x87fpu compar 0123 0123 Compare Real
FCOM ST Mdr DC Mf 2 x87fpu compar 0123 0123 Compare Real
FCOM2 alias ST EST DC 2 00-02 D11 x87fpu compar 0123 0123 Compare Real
FCOM2 alias ST EST DC 2 03+ U15 x87fpu compar 0123 0123 Compare Real
FCOMI ST EST DB 6 PP+ x87fpu compar o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS
FCOMIP ST EST DF 6 PP+ p x87fpu compar o...z.pc .1.. o...z.pc .1.. o....... Compare Floating Point Values and Set EFLAGS and Pop
FCOMP ST ESsr D8 mf 3 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP ST ST1 D8 D9 3 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP ST Mdr DC Mf 3 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP3 alias ST EST DC 3 00-02 D12 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP3 alias ST EST DC 3 03+ U15 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP5 alias ST EST DE 2 00-02 D12 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMP5 alias ST EST DE 2 03+ U15 p x87fpu compar 0123 0123 Compare Real and Pop
FCOMPP ST ST1 DE D9 3 P x87fpu compar 0123 0123 Compare Real and Pop Twice
FCOS ST D9 FF 7 x87fpu trans 0123 .12. 0..3 Cosine
FDECSTP D9 F6 6 x87fpu control 0123 .1.. 0.23 .0.. Decrement Stack-Top Pointer
FDISI 9B DB E1 4 00 x87fpu control Disable NPX Interrupt
FDIV ST Msr D8 mf 6 x87fpu arith 0123 .1.. 0.23 Divide
FDIV ST EST
FDIV ST Mdr DC Mf 6 x87fpu arith 0123 .1.. 0.23 Divide
FDIV EST ST DC 7 x87fpu arith 0123 .1.. 0.23 Divide and Pop
FDIVP EST ST DE 7 p x87fpu arith 0123 .1.. 0.23 Divide and Pop
FDIVP ST1 ST DE F9 7 p x87fpu arith 0123 .1.. 0.23 Divide and Pop
FDIVR ST Msr D8 mf 7 x87fpu arith 0123 .1.. 0.23 Reverse Divide
FDIVR ST EST
FDIVR EST ST DC 6 x87fpu arith 0123 .1.. 0.23 Reverse Divide
FDIVR ST Mdr DC Mf 7 x87fpu arith 0123 .1.. 0.23 Reverse Divide
FDIVRP EST ST DE 6 p x87fpu arith 0123 .1.. 0.23 Reverse Divide and Pop
FDIVRP ST1 ST DE F1 6 p x87fpu arith 0123 .1.. 0.23 Reverse Divide and Pop
FENI 9B DB E0 4 00 x87fpu control Enable NPX Interrupt
FFREE EST DD 0 x87fpu control 0123 0123 Free Floating-Point Register
FFREEP EST DF 0 D14 p x87fpu control 0123 0123 Free Floating-Point Register and Pop
FIADD ST Mdi DA mF 0 x87fpu arith 0123 .1.. 0.23 Add
FIADD ST Mwi DE MF 0 x87fpu arith 0123 .1.. 0.23 Add
FICOM ST Mdi DA mF 2 x87fpu compar 0123 0123 Compare Integer
FICOM ST Mwi DE MF 2 x87fpu compar 0123 0123 Compare Integer
FICOMP ST Mdi DA mF 3 p x87fpu compar 0123 0123 Compare Integer and Pop
FICOMP ST Mwi DE MF 3 p x87fpu compar 0123 0123 Compare Integer and Pop
FIDIV ST Mdi DA mF 6 x87fpu arith 0123 .1.. 0.23 Divide
FIDIV ST Mwi DE MF 6 x87fpu arith 0123 .1.. 0.23 Divide
FIDIVR ST Mdi DA mF 7 x87fpu arith 0123 .1.. 0.23 Reverse Divide
FIDIVR ST Mwi DE MF 7 x87fpu arith 0123 .1.. 0.23 Reverse Divide
FILD ST Mdi DB mF 0 s x87fpu datamov 0123 .1.. 0.23 Load Integer
FILD ST Mwi DF MF 0 s x87fpu datamov 0123 .1.. 0.23 Load Integer
FILD ST Mqi DF 5 s x87fpu datamov 0123 .1.. 0.23 Load Integer
FIMUL ST Mdi DA mF 1 x87fpu arith 0123 .1.. 0.23 Multiply
FIMUL ST Mwi DE MF 1 x87fpu arith 0123 .1.. 0.23 Multiply
FINCSTP D9 F7 6 x87fpu control 0123 .1.. 0.23 .0.. Increment Stack-Top Pointer
FINIT 9B DB E3 4 x87fpu control 0123 0000 Initialize Floating-Point Unit
FIST Mdi ST DB mF 2 x87fpu datamov 0123 .1.. 0.23 Store Integer
FIST Mwi ST DF MF 2 x87fpu datamov 0123 .1.. 0.23 Store Integer
FISTP Mdi ST DB mF 3 p x87fpu datamov 0123 .1.. 0.23 Store Integer and Pop
FISTP Mwi ST DF MF 3 p x87fpu datamov 0123 .1.. 0.23 Store Integer and Pop
FISTP Mqi ST DF 7 p x87fpu datamov 0123 .1.. 0.23 Store Integer and Pop
FISTTP Mdi ST sse3 DB mF 1 P4++ p x87fpu conver 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISTTP Mqi ST sse3 DD 1 P4++ p x87fpu conver 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISTTP Mwi ST sse3 DF MF 1 P4++ p x87fpu conver 0123 .1.. 0.23 .0.. Store Integer with Truncation and Pop
FISUB ST Mdi DA mF 4 x87fpu arith 0123 .1.. 0.23 Subtract
FISUB ST Mwi DE MF 4 x87fpu arith 0123 .1.. 0.23 Subtract
FISUBR ST Mdi DA mF 5 x87fpu arith 0123 .1.. 0.23 Reverse Subtract
FISUBR ST Mwi DE MF 5 x87fpu arith 0123 .1.. 0.23 Reverse Subtract
FLD ST ESsr D9 mf 0 s x87fpu datamov 0123 .1.. 0.23 Load Floating Point Value
FLD ST Mer DB 5 s x87fpu datamov 0123 .1.. 0.23 Load Floating Point Value
FLD ST Mdr DD Mf 0 s x87fpu datamov 0123 .1.. 0.23 Load Floating Point Value
FLD1 ST D9 E8 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant +1.0
FLDCW Mw D9 5 x87fpu control 0123 0123 Load x87 FPU Control Word
FLDENV Me D9 4 x87fpu control 0123 0123 Load x87 FPU Environment
FLDL2E ST D9 EA 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant log2e
FLDL2T ST D9 E9 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant log210
FLDLG2 ST D9 EC 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant log102
FLDLN2 ST D9 ED 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant loge2
FLDPI ST D9 EB 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant π
FLDZ ST D9 EE 5 s x87fpu ldconst 0123 .1.. 0.23 Load Constant +0.0
FMUL ST Msr D8 mf 1 x87fpu arith 0123 .1.. 0.23 Multiply
FMUL ST EST
FMUL ST Mdr DC Mf 1 x87fpu arith 0123 .1.. 0.23 Multiply
FMUL EST ST DC 1 x87fpu arith 0123 .1.. 0.23 Multiply
FMULP EST ST DE 1 p x87fpu arith 0123 .1.. 0.23 Multiply and Pop
FMULP ST1 ST DE C9 1 p x87fpu arith 0123 .1.. 0.23 Multiply and Pop
FNCLEX DB E2 4 x87fpu control 0123 0123 Clear Exceptions
FNDISI DB E1 4 00 x87fpu control Disable NPX Interrupt
FNDISI nop DB E1 4 01+ D9 obsol control Treated as Integer NOP
FNENI DB E0 4 00 x87fpu control Enable NPX Interrupt
FNENI nop DB E0 4 01+ D9 obsol control Treated as Integer NOP
FNINIT DB E3 4 x87fpu control 0123 0000 Initialize Floating-Point Unit
FNOP D9 D0 2 x87fpu control 0123 0123 No Operation
FNSAVE Mst ST ST1 ... DD 6 x87fpu control 0123 0123 0000 Store x87 FPU State
FNSETPM DB E4 4 02 x87fpu control Set Protected Mode
FNSETPM nop DB E4 4 03+ D10 obsol control Treated as Integer NOP
FNSTCW Mw D9 7 x87fpu control 0123 0123 Store x87 FPU Control Word
FNSTENV Me D9 6 x87fpu control 0123 0123 Store x87 FPU Environment
FNSTSW Mw DD 7 x87fpu control 0123 0123 Store x87 FPU Status Word
FNSTSW AX DF E0 4 02+ x87fpu control 0123 0123 Store x87 FPU Status Word
FPATAN ST1 ST D9 F3 6 p x87fpu trans 0123 .1.. 0.23 Partial Arctangent and Pop
FPREM ST ST1 D9 F8 7 x87fpu arith 0123 0123 Partial Remainder (for compatibility with i8087 and i287)
FPREM1 ST ST1 D9 F5 6 x87fpu arith 0123 0123 IEEE Partial Remainder
FPTAN ST D9 F2 6 s x87fpu trans 0123 .12. 0..3 Partial Tangent
FRNDINT ST D9 FC 7 x87fpu arith 0123 .1.. 0.23 Round to Integer
FRSTOR ST ST1 ST2 ... DD 4 x87fpu control 0123 0123 Restore x87 FPU State
FS FS 64 03+ prefix segreg FS segment override prefix
FSAVE Mst ST ST1 ... 9B DD 6 x87fpu control 0123 0123 0000 Store x87 FPU State
FSCALE ST ST1 D9 FD 7 x87fpu arith 0123 .1.. 0.23 Scale
FSETPM 9B DB E4 4 02 x87fpu control Set Protected Mode
FSIN ST D9 FE 7 x87fpu trans 0123 .12. 0..3 Sine
FSINCOS ST D9 FB 7 s x87fpu trans 0123 .12. 0..3 Sine and Cosine
FSQRT ST D9 FA 7 x87fpu arith 0123 .1.. 0.23 Square Root
FST Msr ST D9 mf 2 x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value
FST Mdr ST DD Mf 2 x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value
FST ST EST DD 2 x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value
FSTCW Mw 9B D9 7 x87fpu control 0123 0123 Store x87 FPU Control Word
FSTENV Me 9B D9 6 x87fpu control 0123 0123 Store x87 FPU Environment
FSTP Msr ST D9 mf 3 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP Mer ST DB 7 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP Mdr ST DD Mf 3 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP ST EST DD 3 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP1 part alias8 EST ST D9 3 00-02 D7 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP1 part alias8 EST ST D9 3 03+ U15 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP8 alias EST ST DF 2 00-02 D7 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP8 alias EST ST DF 2 03+ U15 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP9 alias EST ST DF 3 00-02 D7 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTP9 alias EST ST DF 3 03+ U15 p x87fpu datamov 0123 .1.. 0.23 Store Floating Point Value and Pop
FSTSW Mw 9B DD 7 x87fpu control 0123 0123 Store x87 FPU Status Word
FSTSW AX 9B DF E0 4 02+ x87fpu control 0123 0123 Store x87 FPU Status Word
FSUB ST Msr D8 mf 4 x87fpu arith 0123 .1.. 0.23 Subtract
FSUB ST EST
FSUB ST Mdr DC Mf 4 x87fpu arith 0123 .1.. 0.23 Subtract
FSUB EST ST DC 5 x87fpu arith 0123 .1.. 0.23 Subtract
FSUBP EST ST DE 5 p x87fpu arith 0123 .1.. 0.23 Subtract and Pop
FSUBP ST1 ST DE E9 5 p x87fpu arith 0123 .1.. 0.23 Subtract and Pop
FSUBR ST Msr D8 mf 5 x87fpu arith 0123 .1.. 0.23 Reverse Subtract
FSUBR ST EST
FSUBR EST ST DC 4 x87fpu arith 0123 .1.. 0.23 Reverse Subtract
FSUBR ST Mdr DC Mf 5 x87fpu arith 0123 .1.. 0.23 Reverse Subtract
FSUBRP EST ST DE 4 p x87fpu arith 0123 .1.. 0.23 Reverse Subtract and Pop
FSUBRP ST1 ST DE E1 4 p x87fpu arith 0123 .1.. 0.23 Reverse Subtract and Pop
FTST ST D9 E4 4 x87fpu compar 0123 0123 Test
FUCOM ST EST DD 4 03+ x87fpu compar 0123 0123 Unordered Compare Floating Point Values
FUCOM ST ST1 DD E1 4 03+ x87fpu compar 0123 0123 Unordered Compare Floating Point Values
FUCOMI ST EST DB 5 PP+ x87fpu compar o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS
FUCOMIP ST EST DF 5 PP+ p x87fpu compar o...z.pc .1.. o...z.pc .1.. o....... Unordered Compare Floating Point Values and Set EFLAGS and Pop
FUCOMP ST EST DD 5 03+ p x87fpu compar 0123 0123 Unordered Compare Floating Point Values and Pop
FUCOMP ST ST1 DD E9 5 03+ p x87fpu compar 0123 0123 Unordered Compare Floating Point Values and Pop
FUCOMPP ST ST1 DA E9 5 03+ P x87fpu compar 0123 0123 Unordered Compare Floating Point Values and Pop Twice
FWAIT 9B x87fpu control 0123 0123 Check pending unmasked floating-point exceptions
WAIT
FXAM ST D9 E5 4 x87fpu 0123 0123 Examine
FXCH ST EST D9 mf 1 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXCH ST ST1 D9 C9 1 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXCH4 alias ST EST DD 1 00-02 D13 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXCH4 alias ST EST DD 1 03+ U15 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXCH7 alias ST EST DF 1 00-02 D13 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXCH7 alias ST EST DF 1 03+ U15 x87fpu datamov 0123 .1.. 0.23 Exchange Register Contents
FXRSTOR ST ST1 ST2 ... 0F AE 1 P2++ sm Restore x87 FPU, MMX, XMM, and MXCSR State
FXSAVE Mstx ST ST1 ... 0F AE 0 P2++ sm Save x87 FPU, MMX, XMM, and MXCSR State
FXTRACT ST D9 F4 6 s x87fpu arith 0123 .1.. 0.23 Extract Exponent and Significand
FYL2X ST1 ST D9 F1 6 p x87fpu trans 0123 .1.. 0.23 Compute y × log2x and Pop
FYL2XP1 ST1 ST D9 F9 7 p x87fpu trans 0123 .1.. 0.23 Compute y × log2(x+1) and Pop
GETSEC EAX smx 0F 37 C2++ D24 GETSEC Leaf Functions
GS GS 65 03+ prefix segreg GS segment override prefix
HADDPD Vpd Wpd sse3 66 0F 7C r P4++ simdfp arith Packed Double-FP Horizontal Add
HADDPS Vps Wps sse3 F2 0F 7C r P4++ simdfp arith Packed Single-FP Horizontal Add
HINT_NOP Ev 0F 18 PP-P2 M22 gen control Hintable NOP
HINT_NOP Ev 0F 18 4 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 18 5 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 18 6 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 18 7 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 19 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1A PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1B PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1C PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1D PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1E PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F PP-P2 M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 1 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 2 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 3 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 4 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 5 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 6 PP+ M22 gen control Hintable NOP
HINT_NOP Ev 0F 1F 7 PP+ M22 gen control Hintable NOP
HLT F4 0 system Halt
HSUBPD Vpd Wpd sse3 66 0F 7D r P4++ simdfp arith Packed Double-FP Horizontal Subtract
HSUBPS Vps Wps sse3 F2 0F 7D r P4++ simdfp arith Packed Single-FP Horizontal Subtract
IDIV AL AH AX Eb F6 w 7 gen arith binary o..szapc o..szapc Signed Divide
IDIV eDX eAX Ev F7 W 7 gen arith binary o..szapc o..szapc Signed Divide
IMUL Gv Ev Iv 69 r 01+ gen arith binary o..szapc o......c ...szap. Signed Multiply
IMUL Gv Ev Ibs 6B S r 01+ gen arith binary o..szapc o......c ...szap. Signed Multiply
IMUL AX AL Eb F6 w 5 gen arith binary o..szapc o......c ...szap. Signed Multiply
IMUL eDX eAX Ev F7 W 5 gen arith binary o..szapc o......c ...szap. Signed Multiply
IMUL Gv Ev 0F AF DW r 03+ gen arith binary o..szapc o......c ...szap. Signed Multiply
IN AL Ib E4 w f1 gen inout Input from Port
IN eAX Ib E5 W f1 gen inout Input from Port
IN AL DX EC w f1 gen inout Input from Port
IN eAX DX ED W f1 gen inout Input from Port
INC Zv 40 +r gen arith binary o..szap. o..szap. Increment by 1
INC Eb FE w 0 L gen arith binary o..szap. o..szap. Increment by 1
INC Ev FF W 0 L gen arith binary o..szap. o..szap. Increment by 1
INS Yb DX 6C w 01+ f1 gen inout string .d...... Input from Port to String
INSB Yb DX
INS Ywo DX 6D W 01+ f1 gen inout string .d...... Input from Port to String
INSW Ywo DX
INS Yv DX 6D W 03+ f1 gen inout string .d...... Input from Port to String
INSD Ydo DX
INSERTPS Vps Md Ib sse41 66 0F 3A 21 r C2++ D32 simdfp datamov Insert Packed Single-FP Value
INSERTPS Vps Ups Ib
INT alias 3 Fv CC f gen break stack ..i..... ..i..... ..i..... Call to Interrupt Procedure
INT Ib Fv CD f gen break stack ..i..... ..i..... ..i..... Call to Interrupt Procedure
INT1 part alias16 Fv F1 03+ U16 gen break stack ..i..... ..i..... ..i..... Call to Interrupt Procedure
ICEBP part alias16 Fv
INTO Fv CE f gen break stack o....... ..i..... ..i..... ..i..... Call to Interrupt Procedure
INVD 0F 08 04+ 0 system Invalidate Internal Caches
INVEPT Gd Mdq vmx 66 0F 38 80 r C2++ D31 P 0 o..szapc o..szapc Invalidate Translations Derived from EPT
INVLPG M 0F 01 7 04+ 0 system Invalidate TLB Entry
INVVPID Gd Mdq vmx 66 0F 38 81 r C2++ D31 P 0 o..szapc o..szapc Invalidate Translations Based on VPID
IRET Fwo CF f gen break stack Interrupt Return
IRETD Fdo CF 03+ f gen break stack Interrupt Return
JB Jbs 72 ttTn gen branch cond .......c Jump short if below/not above or equal/carry (CF=1)
JNAE Jbs
JC Jbs
JB Jv 0F 82 ttTn 03+ gen branch cond .......c Jump near if below/not above or equal/carry (CF=1)
JNAE Jv
JC Jv
JBE Jbs 76 tTTn gen branch cond ....z..c Jump short if below or equal/not above (CF=1 OR ZF=1)
JNA Jbs
JBE Jv 0F 86 tTTn 03+ gen branch cond ....z..c Jump near if below or equal/not above (CF=1 OR ZF=1)
JNA Jv
JCXZ Jbs CX E3 gen branch cond Jump short if eCX register is 0
JECXZ Jbs ECX
JL Jbs 7C TTtn gen branch cond o..s.... Jump short if less/not greater (SF!=OF)
JNGE Jbs
JL Jv 0F 8C TTtn 03+ gen branch cond o..s.... Jump near if less/not greater (SF!=OF)
JNGE Jv
JLE Jbs 7E TTTn gen branch cond o..sz... Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG Jbs
JLE Jv 0F 8E TTTn 03+ gen branch cond o..sz... Jump near if less or equal/not greater ((ZF=1) OR (SF!=OF))
JNG Jv
JMP Jv E9 gen branch Jump
JMP Jbs EB gen branch Jump
JMP Ev FF 4 gen branch Jump
JMPE 0F 00 6 IT+ system branch Jump to IA-64 Instruction Set
JMPE 0F B8 IT+ system branch Jump to IA-64 Instruction Set
JMPF Ap EA gen branch Jump
JMPF Mp FF 5 gen branch Jump
JNB Jbs 73 ttTN gen branch cond .......c Jump short if not below/above or equal/not carry (CF=0)
JAE Jbs
JNC Jbs
JNB Jv 0F 83 ttTN 03+ gen branch cond .......c Jump near if not below/above or equal/not carry (CF=0)
JAE Jv
JNC Jv
JNBE Jbs 77 tTTN gen branch cond ....z..c Jump short if not below or equal/above (CF=0 AND ZF=0)
JA Jbs
JNBE Jv 0F 87 tTTN 03+ gen branch cond ....z..c Jump near if not below or equal/above (CF=0 AND ZF=0)
JA Jv
JNL Jbs 7D TTtN gen branch cond o..s.... Jump short if not less/greater or equal (SF=OF)
JGE Jbs
JNL Jv 0F 8D TTtN 03+ gen branch cond o..s.... Jump near if not less/greater or equal (SF=OF)
JGE Jv
JNLE Jbs 7F TTTN gen branch cond o..sz... Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG Jbs
JNLE Jv 0F 8F TTTN 03+ gen branch cond o..sz... Jump near if not less nor equal/greater ((ZF=0) AND (SF=OF))
JG Jv
JNO Jbs 71 tttN gen branch cond o....... Jump short if not overflow (OF=0)
JNO Jv 0F 81 tttN 03+ gen branch cond o....... Jump near if not overflow (OF=0)
JNP Jbs 7B TtTN gen branch cond ......p. Jump short if not parity/parity odd (PF=0)
JPO Jbs
JNP Jv 0F 8B TtTN 03+ gen branch cond ......p. Jump near if not parity/parity odd (PF=0)
JPO Jv
JNS Jbs 79 TttN gen branch cond ...s.... Jump short if not sign (SF=0)
JNS Jv 0F 89 TttN 03+ gen branch cond ...s.... Jump near if not sign (SF=0)
JNZ Jbs 75 tTtN gen branch cond ....z... Jump short if not zero/not equal (ZF=0)
JNE Jbs
JNZ Jv 0F 85 tTtN 03+ gen branch cond ....z... Jump near if not zero/not equal (ZF=0)
JNE Jv
JO Jbs 70 tttn gen branch cond o....... Jump short if overflow (OF=1)
JO Jv 0F 80 tttn 03+ gen branch cond o....... Jump near if overflow (OF=1)
JP Jbs 7A TtTn gen branch cond ......p. Jump short if parity/parity even (PF=1)
JPE Jbs
JP Jv 0F 8A TtTn 03+ gen branch cond ......p. Jump near if parity/parity even (PF=1)
JPE Jv
JS Jbs 78 Tttn gen branch cond ...s.... Jump short if sign (SF=1)
JS Jv 0F 88 Tttn 03+ gen branch cond ...s.... Jump near if sign (SF=1)
JZ Jbs 74 tTtn gen branch cond ....z... Jump short if zero/equal (ZF=1)
JE Jbs
JZ Jv 0F 84 tTtn 03+ gen branch cond ....z... Jump near if zero/equal (ZF=1)
JE Jv
LAHF AH 9F gen datamov flgctrl ...szapc Load Status Flags into AH Register
LAR Gv Mw 0F 02 r 02+ P system ....z... ....z... Load Access Rights Byte
LAR Gv Rv
LDDQU Vdq Mdq sse3 F2 0F F0 r P4++ cachect Load Unaligned Integer 128 Bits
LDMXCSR Md sse1 0F AE 2 P3+ mxcsrsm Load MXCSR Register
LDS DS Gv Mp C5 r gen datamov segreg Load Far Pointer
LEA Gv M 8D r gen datamov Load Effective Address
LEAVE eBP C9 01+ gen stack High Level Procedure Exit
LES ES Gv Mp C4 r gen datamov segreg Load Far Pointer
LFENCE sse2 0F AE 5 P4+ order Load Fence
LFS FS Gv Mp 0F B4 Sre r 03+ gen datamov segreg Load Far Pointer
LGDT GDTR Ms 0F 01 2 02+ 0 system Load Global Descriptor Table Register
LGS GS Gv Mp 0F B5 SrE r 03+ gen datamov segreg Load Far Pointer
LIDT IDTR Ms 0F 01 3 02+ 0 system Load Interrupt Descriptor Table Register
LLDT LDTR Ew 0F 00 2 02+ P 0 system Load Local Descriptor Table Register
LMSW MSW Ew 0F 01 6 02+ 0 system Load Machine Status Word
LOADALL AX CX DX ... 0F 05 02 U20 P system branch Load All of the CPU Registers
LOADALL EAX ECX EDX ... 0F 07 03 U20 P system branch Load All of the CPU Registers
LOCK F0 prefix Assert LOCK# Signal Prefix
LODS AL Xb AC w gen datamov string .d...... Load String
LODSB AL Xb
LODS AX Xwo AD W gen datamov string .d...... Load String
LODSW AX Xwo
LODS eAX Xv AD W 03+ gen datamov string .d...... Load String
LODSD EAX Xdo
LOOP eCX Jbs E2 gen branch cond Decrement count; Jump short if count!=0
LOOPNZ eCX Jbs E0 gen branch cond ....z... Decrement count; Jump short if count!=0 and ZF=0
LOOPNE eCX Jbs
LOOPZ eCX Jbs E1 gen branch cond ....z... Decrement count; Jump short if count!=0 and ZF=1
LOOPE eCX Jbs
LSL Gv Mw 0F 03 r 02+ P system ....z... ....z... Load Segment Limit
LSL Gv Rv
LSS SS Gv Mp 0F B2 sRe r 03+ gen datamov segreg Load Far Pointer
LTR TR Ew 0F 00 3 02+ P 0 system Load Task Register
MASKMOVDQU BDdq Vdq Udq sse2 66 0F F7 r P4+ cachect Store Selected Bytes of Double Quadword
MASKMOVQ BDq Pq Nq sse1 0F F7 r P3+ D30 cachect Store Selected Bytes of Quadword
MAXPD Vpd Wpd sse2 66 0F 5F r P4+ pcksclr arith Return Maximum Packed Double-FP Values
MAXPS Vps Wps sse1 0F 5F r P3+ simdfp arith Return Maximum Packed Single-FP Values
MAXSD Vsd Wsd sse2 F2 0F 5F r P4+ pcksclr arith Return Maximum Scalar Double-FP Value
MAXSS Vss Wss sse1 F3 0F 5F r P3+ simdfp arith Return Maximum Scalar Single-FP Value
MFENCE sse2 0F AE 6 P4+ order Memory Fence
MINPD Vpd Wpd sse2 66 0F 5D r P4+ pcksclr arith Return Minimum Packed Double-FP Values
MINPS Vps Wps sse1 0F 5D r P3+ simdfp arith Return Minimum Packed Single-FP Values
MINSD Vsd Wsd sse2 F2 0F 5D r P4+ pcksclr arith Return Minimum Scalar Double-FP Value
MINSS Vss Wss sse1 F3 0F 5D r P3+ simdfp arith Return Minimum Scalar Single-FP Value
MONITOR BAb ECX EDX sse3 0F 01 C8 1 P4++ 0 sync Set Up Monitor Address
MOV Eb Gb 88 dw r gen datamov Move
MOV Ev Gv 89 dW r gen datamov Move
MOV Gb Eb 8A Dw r gen datamov Move
MOV Gv Ev 8B DW r gen datamov Move
MOV Mw Sw 8C d r gen datamov Move
MOV Rv Sw
MOV Sw Ew 8E D r gen datamov Move
MOV AL Ob A0 w gen datamov Move
MOV eAX Ov A1 W gen datamov Move
MOV Ob AL A2 w gen datamov Move
MOV Ov eAX A3 W gen datamov Move
MOV Zb Ib B0 +r gen datamov Move
MOV Zv Iv B8 +r gen datamov Move
MOV Eb Ib C6 w 0 gen datamov Move
MOV Ev Iv C7 W 0 gen datamov Move
MOV Rd Cd 0F 20 r 03+ 0 system o..szapc o..szapc Move to/from Control Registers
MOV Hd Cd 0F 20 r 03+ U23 0 system o..szapc o..szapc Move to/from Control Registers
MOV Rd Dd 0F 21 r 03+ 0 system o..szapc o..szapc Move to/from Debug Registers
MOV Hd Dd 0F 21 r 03+ U23 0 system o..szapc o..szapc Move to/from Debug Registers
MOV Cd Rd 0F 22 r 03+ 0 system o..szapc o..szapc Move to/from Control Registers
MOV Cd Hd 0F 22 r 03+ U23 0 system o..szapc o..szapc Move to/from Control Registers
MOV Dd Rd 0F 23 r 03+ 0 system o..szapc o..szapc Move to/from Debug Registers
MOV Dq Hq 0F 23 r 03+ U23 0 system o..szapc o..szapc Move to/from Debug Registers
MOV Rd Td 0F 24 r 03-04 0 system o..szapc o..szapc Move to/from Test Registers
MOV Hd Td 0F 24 r 03-04 U23 0 system o..szapc o..szapc Move to/from Test Registers
MOV Td Rd 0F 26 r 03-04 0 system o..szapc o..szapc Move to/from Test Registers
MOV Td Hd 0F 26 r 03-04 U23 0 system o..szapc o..szapc Move to/from Test Registers
MOVAPD Vpd Wpd sse2 66 0F 28 r P4+ pcksclr datamov Move Aligned Packed Double-FP Values
MOVAPD Wpd Vpd sse2 66 0F 29 r P4+ pcksclr datamov Move Aligned Packed Double-FP Values
MOVAPS Vps Wps sse1 0F 28 r P3+ simdfp datamov Move Aligned Packed Single-FP Values
MOVAPS Wps Vps sse1 0F 29 r P3+ simdfp datamov Move Aligned Packed Single-FP Values
MOVBE Gv Mv 0F 38 F0 r C2++ gen datamov Move Data After Swapping Bytes
MOVBE Mv Gv 0F 38 F1 r C2++ gen datamov Move Data After Swapping Bytes
MOVD Pq Ed mmx 0F 6E r PX+ datamov Move Doubleword
MOVD Vdq Ed sse2 66 0F 6E r P4+ simdint datamov Move Doubleword
MOVD Ed Pq mmx 0F 7E r PX+ datamov Move Doubleword
MOVD Ed Vdq sse2 66 0F 7E r P4+ simdint datamov Move Doubleword
MOVDDUP Vq Wq sse3 F2 0F 12 r P4++ simdfp datamov Move One Double-FP and Duplicate
MOVDQ2Q Pq Uq sse2 F2 0F D6 r P4+ simdint datamov Move Quadword from XMM to MMX Technology Register
MOVDQA Vdq Wdq sse2 66 0F 6F r P4+ simdint datamov Move Aligned Double Quadword
MOVDQA Wdq Vdq sse2 66 0F 7F r P4+ simdint datamov Move Aligned Double Quadword
MOVDQU Vdq Wdq sse2 F3 0F 6F r P4+ simdint datamov Move Unaligned Double Quadword
MOVDQU Wdq Vdq sse2 F3 0F 7F r P4+ simdint datamov Move Unaligned Double Quadword
MOVHLPS Vq Uq sse1 0F 12 r P3+ simdfp datamov Move Packed Single-FP Values High to Low
MOVHPD Vq Mq sse2 66 0F 16 r P4+ pcksclr datamov Move High Packed Double-FP Value
MOVHPD Mq Vq sse2 66 0F 17 r P4+ pcksclr datamov Move High Packed Double-FP Value
MOVHPS Vq Mq sse1 0F 16 r P3+ simdfp datamov Move High Packed Single-FP Values
MOVHPS Mq Vq sse1 0F 17 r P3+ simdfp datamov Move High Packed Single-FP Values
MOVLHPS Vq Uq sse1 0F 16 r P3+ simdfp datamov Move Packed Single-FP Values Low to High
MOVLPD Vq Mq sse2 66 0F 12 r P4+ pcksclr datamov Move Low Packed Double-FP Value
MOVLPD Mq Vq sse2 66 0F 13 r P4+ pcksclr datamov Move Low Packed Double-FP Value
MOVLPS Vq Mq sse1 0F 12 r P3+ simdfp datamov Move Low Packed Single-FP Values
MOVLPS Mq Vq sse1 0F 13 r P3+ simdfp datamov Move Low Packed Single-FP Values
MOVMSKPD Gd Upd sse2 66 0F 50 r P4+ pcksclr datamov Extract Packed Double-FP Sign Mask
MOVMSKPS Gd Ups sse1 0F 50 r P3+ simdfp datamov Extract Packed Single-FP Sign Mask
MOVNTDQ Mdq Vdq sse2 66 0F E7 r P4+ cachect Store Double Quadword Using Non-Temporal Hint
MOVNTDQA Vdq Mdq sse41 66 0F 38 2A r C2++ D32 cachect Load Double Quadword Non-Temporal Aligned Hint
MOVNTI Md Gd sse2 0F C3 r P4+ cachect Store Doubleword Using Non-Temporal Hint
MOVNTPD Mpd Vpd sse2 66 0F 2B r P4+ cachect Store Packed Double-FP Values Using Non-Temporal Hint
MOVNTPS Mps Vps sse1 0F 2B r P3+ cachect Store Packed Single-FP Values Using Non-Temporal Hint
MOVNTQ Mq Pq sse1 0F E7 r P3+ cachect Store of Quadword Using Non-Temporal Hint
MOVQ Pq Qq mmx 0F 6F r PX+ datamov Move Quadword
MOVQ Vq Wq sse2 F3 0F 7E r P4+ simdint datamov Move Quadword
MOVQ Qq Pq mmx 0F 7F r PX+ datamov Move Quadword
MOVQ Wq Vq sse2 66 0F D6 r P4+ simdint datamov Move Quadword
MOVQ2DQ Vdq Nq sse2 F3 0F D6 r P4+ simdint datamov Move Quadword from MMX Technology to XMM Register
MOVS Yb Xb A4 w gen datamov string .d...... Move Data from String to String
MOVSB Yb Xb
MOVS Ywo Xwo A5 W gen datamov string .d...... Move Data from String to String
MOVSW Ywo Xwo
MOVS Yv Xv A5 W 03+ gen datamov string .d...... Move Data from String to String
MOVSD Ydo Xdo
MOVSD Vsd Wsd sse2 F2 0F 10 r P4+ pcksclr datamov Move Scalar Double-FP Value
MOVSD Wsd Vsd sse2 F2 0F 11 r P4+ pcksclr datamov Move Scalar Double-FP Value
MOVSHDUP Vq Wq sse3 F3 0F 16 r P4++ simdfp datamov Move Packed Single-FP High and Duplicate
MOVSLDUP Vq Wq sse3 F3 0F 12 r P4++ simdfp datamov Move Packed Single-FP Low and Duplicate
MOVSS Vss Wss sse1 F3 0F 10 r P3+ simdfp datamov Move Scalar Single-FP Values
MOVSS Wss Vss sse1 F3 0F 11 r P3+ simdfp datamov Move Scalar Single-FP Values
MOVSX Gv Eb 0F BE Dw r 03+ gen conver Move with Sign-Extension
MOVSX Gv Ew 0F BF DW r 03+ gen conver Move with Sign-Extension
MOVUPD Vpd Wpd sse2 66 0F 10 r P4+ pcksclr datamov Move Unaligned Packed Double-FP Value
MOVUPD Wpd Vpd sse2 66 0F 11 r P4+ pcksclr datamov Move Unaligned Packed Double-FP Values
MOVUPS Vps Wps sse1 0F 10 r P3+ simdfp datamov Move Unaligned Packed Single-FP Values
MOVUPS Wps Vps sse1 0F 11 r P3+ simdfp datamov Move Unaligned Packed Single-FP Values
MOVZX Gv Eb 0F B6 Dw r 03+ gen conver Move with Zero-Extend
MOVZX Gv Ew 0F B7 DW r 03+ gen conver Move with Zero-Extend
MPSADBW Vdq Wdq Ib sse41 66 0F 3A 42 r C2++ D32 simdint arith Compute Multiple Packed Sums of Absolute Difference
MUL AX AL Eb F6 w 4 gen arith binary o..szapc o......c ...szap. Unsigned Multiply
MUL eDX eAX Ev F7 W 4 gen arith binary o..szapc o......c ...szap. Unsigned Multiply
MULPD Vpd Wpd sse2 66 0F 59 r P4+ pcksclr arith Multiply Packed Double-FP Values
MULPS Vps Wps sse1 0F 59 r P3+ simdfp arith Multiply Packed Single-FP Values
MULSD Vsd Wsd sse2 F2 0F 59 r P4+ pcksclr arith Multiply Scalar Double-FP Values
MULSS Vss Wss sse1 F3 0F 59 r P3+ simdfp arith Multiply Scalar Single-FP Value
MWAIT EAX ECX sse3 0F 01 C9 1 P4++ 0 sync Monitor Wait
NEG Eb F6 w 3 L gen arith binary o..szapc o..szapc Two's Complement Negation
NEG Ev F7 W 3 L gen arith binary o..szapc o..szapc Two's Complement Negation
NOP 90 D3 gen control No Operation
NOP nop F3 90 00-P3 D4 gen control No Operation
NOP Ev 0F 0D PP+ M21 gen control No Operation
NOP Ev 0F 1F 0 P4++ gen control No Operation
NOT Eb F6 w 2 L gen logical One's Complement Negation
NOT Ev F7 W 2 L gen logical One's Complement Negation
NTAKEN 2E P4 D2 prefix branch cond Branch not taken prefix (only with Jcc instructions)
OR Eb Gb 08 dw r L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Ev Gv 09 dW r L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Gb Eb 0A Dw r gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Gv Ev 0B DW r gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR AL Ib 0C w gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR eAX Iv 0D W gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Eb Ib 80 w 1 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Ev Iv 81 W 1 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR alias Eb Ib 82 w 1 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
OR Ev Ibs 83 SW 1 03+ L gen logical o..szapc o..sz.pc .....a.. o......c Logical Inclusive OR
ORPD Vpd Wpd sse2 66 0F 56 r P4+ pcksclr logical Bitwise Logical OR of Double-FP Values
ORPS Vps Wps sse1 0F 56 r P3+ simdfp logical Bitwise Logical OR of Single-FP Values
OUT Ib AL E6 w f1 gen inout Output to Port
OUT Ib eAX E7 W f1 gen inout Output to Port
OUT DX AL EE w f1 gen inout Output to Port
OUT DX eAX EF W f1 gen inout Output to Port
OUTS DX Xb 6E w 01+ f1 gen inout string .d...... Output String to Port
OUTSB DX Xb
OUTS DX Xwo 6F W 01+ f1 gen inout string .d...... Output String to Port
OUTSW DX Xwo
OUTS DX Xv 6F W 03+ f1 gen inout string .d...... Output String to Port
OUTSD DX Xdo
PABSB Pq Qq ssse3 0F 38 1C r C2+ simdint Packed Absolute Value
PABSB Vdq Wdq ssse3 66 0F 38 1C r C2+ simdint Packed Absolute Value
PABSD Pq Qq ssse3 0F 38 1E r C2+ simdint Packed Absolute Value
PABSD Vdq Wdq ssse3 66 0F 38 1E r C2+ simdint Packed Absolute Value
PABSW Pq Qq ssse3 0F 38 1D r C2+ simdint Packed Absolute Value
PABSW Vdq Wdq ssse3 66 0F 38 1D r C2+ simdint Packed Absolute Value
PACKSSDW Pq Qq mmx 0F 6B r PX+ conver Pack with Signed Saturation
PACKSSDW Vdq Wdq sse2 66 0F 6B r P4+ simdint conver Pack with Signed Saturation
PACKSSWB Pq Qd mmx 0F 63 r PX+ conver Pack with Signed Saturation
PACKSSWB Vdq Wdq sse2 66 0F 63 r P4+ simdint conver Pack with Signed Saturation
PACKUSDW Vdq Wdq sse41 66 0F 38 2B r C2++ D32 simdint conver Pack with Unsigned Saturation
PACKUSWB Pq Qq mmx 0F 67 r PX+ conver Pack with Unsigned Saturation
PACKUSWB Vdq Wdq sse2 66 0F 67 r P4+ simdint conver Pack with Unsigned Saturation
PADDB Pq Qq mmx 0F FC r PX+ arith Add Packed Integers
PADDB Vdq Wdq sse2 66 0F FC r P4+ simdint arith Add Packed Integers
PADDD Pq Qq mmx 0F FE r PX+ arith Add Packed Integers
PADDD Vdq Wdq sse2 66 0F FE r P4+ simdint arith Add Packed Integers
PADDQ Pq Qq sse2 0F D4 r PX+ simdint arith Add Packed Quadword Integers
PADDQ Vdq Wdq sse2 66 0F D4 r P4+ simdint arith Add Packed Quadword Integers
PADDSB Pq Qq mmx 0F EC r PX+ arith Add Packed Signed Integers with Signed Saturation
PADDSB Vdq Wdq sse2 66 0F EC r P4+ simdint arith Add Packed Signed Integers with Signed Saturation
PADDSW Pq Qq mmx 0F ED r PX+ arith Add Packed Signed Integers with Signed Saturation
PADDSW Vdq Wdq sse2 66 0F ED r P4+ simdint arith Add Packed Signed Integers with Signed Saturation
PADDUSB Pq Qq mmx 0F DC r PX+ arith Add Packed Unsigned Integers with Unsigned Saturation
PADDUSB Vdq Wdq sse2 66 0F DC r P4+ simdint arith Add Packed Unsigned Integers with Unsigned Saturation
PADDUSW Pq Qq mmx 0F DD r PX+ arith Add Packed Unsigned Integers with Unsigned Saturation
PADDUSW Vdq Wdq sse2 66 0F DD r P4+ simdint arith Add Packed Unsigned Integers with Unsigned Saturation
PADDW Pq Qq mmx 0F FD r PX+ arith Add Packed Integers
PADDW Vdq Wdq sse2 66 0F FD r P4+ simdint arith Add Packed Integers
PALIGNR Pq Qq ssse3 0F 3A 0F r C2+ simdint Packed Align Right
PALIGNR Vdq Wdq ssse3 66 0F 3A 0F r C2+ simdint Packed Align Right
PAND Pq Qd mmx 0F DB r PX+ logical Logical AND
PAND Vdq Wdq sse2 66 0F DB r P4+ simdint logical Logical AND
PANDN Pq Qq mmx 0F DF r PX+ logical Logical AND NOT
PANDN Vdq Wdq sse2 66 0F DF r P4+ simdint logical Logical AND NOT
PAUSE sse2 F3 90 P4+ cachect Spin Loop Hint
PAVGB Pq Qq sse1 0F E0 r P3+ simdint Average Packed Integers
PAVGB Vdq Wdq sse1 66 0F E0 r P3+ simdint Average Packed Integers
PAVGW Pq Qq sse1 0F E3 r P3+ simdint Average Packed Integers
PAVGW Vdq Wdq sse1 66 0F E3 r P3+ simdint Average Packed Integers
PBLENDVB Vdq Wdq XMM0 sse41 66 0F 38 10 r C2++ D32 simdint datamov Variable Blend Packed Bytes
PBLENDW Vdq Wdq Ib sse41 66 0F 3A 0E r C2++ D32 simdint datamov Blend Packed Words
PCMPEQB Pq Qq mmx 0F 74 r PX+ compar Compare Packed Data for Equal
PCMPEQB Vdq Wdq sse2 66 0F 74 r P4+ simdint compar Compare Packed Data for Equal
PCMPEQD Pq Qq mmx 0F 76 r PX+ compar Compare Packed Data for Equal
PCMPEQD Vdq Wdq sse2 66 0F 76 r P4+ simdint compar Compare Packed Data for Equal
PCMPEQQ Vdq Wdq sse41 66 0F 38 29 r C2++ D32 simdint compar Compare Packed Qword Data for Equal
PCMPEQW Pq Qq mmx 0F 75 r PX+ compar Compare Packed Data for Equal
PCMPEQW Vdq Wdq sse2 66 0F 75 r P4+ simdint compar Compare Packed Data for Equal
PCMPESTRI ECX Vdq Wdq ... sse42 66 0F 3A 61 r C2++ D32 strtxt o..szapc o..szapc .....ap. Packed Compare Explicit Length Strings, Return Index
PCMPESTRM XMM0 Vdq Wdq ... sse42 66 0F 3A 60 r C2++ D32 strtxt o..szapc o..szapc .....ap. Packed Compare Explicit Length Strings, Return Mask
PCMPGTB Pq Qd mmx 0F 64 r PX+ compar Compare Packed Signed Integers for Greater Than
PCMPGTB Vdq Wdq sse2 66 0F 64 r P4+ simdint compar Compare Packed Signed Integers for Greater Than
PCMPGTD Pq Qd mmx 0F 66 r PX+ compar Compare Packed Signed Integers for Greater Than
PCMPGTD Vdq Wdq sse2 66 0F 66 r P4+ simdint compar Compare Packed Signed Integers for Greater Than
PCMPGTQ Vdq Wdq sse42 66 0F 38 37 r C2++ D32 simdint compar Compare Packed Qword Data for Greater Than
PCMPGTW Pq Qd mmx 0F 65 r PX+ compar Compare Packed Signed Integers for Greater Than
PCMPGTW Vdq Wdq sse2 66 0F 65 r P4+ simdint compar Compare Packed Signed Integers for Greater Than
PCMPISTRI ECX Vdq Wdq Ib sse42 66 0F 3A 63 r C2++ D32 strtxt o..szapc o..szapc .....ap. Packed Compare Implicit Length Strings, Return Index
PCMPISTRM XMM0 Vdq Wdq Ib sse42 66 0F 3A 62 r C2++ D32 strtxt o..szapc o..szapc .....ap. Packed Compare Implicit Length Strings, Return Mask
PEXTRB Mb Vdq Ib sse41 66 0F 3A 14 r C2++ D32 simdint datamov Extract Byte
PEXTRB Rd Vdq Ib
PEXTRD Ed Vdq Ib sse41 66 0F 3A 16 r C2++ D32 simdint datamov Extract Dword/Qword
PEXTRQ Eqp Vdq Ib
PEXTRW Mw Vdq Ib sse41 66 0F 3A 15 r C2++ D32 simdint datamov Extract Word
PEXTRW Rd Vdq Ib
PEXTRW Gd Nq Ib sse1 0F C5 r P3+ simdint Extract Word
PEXTRW Gd Udq Ib sse1 66 0F C5 r P3+ simdint Extract Word
PHADDD Pq Qq ssse3 0F 38 02 r C2+ simdint Packed Horizontal Add
PHADDD Vdq Wdq ssse3 66 0F 38 02 r C2+ simdint Packed Horizontal Add
PHADDSW Pq Qq ssse3 0F 38 03 r C2+ simdint Packed Horizontal Add and Saturate
PHADDSW Vdq Wdq ssse3 66 0F 38 03 r C2+ simdint Packed Horizontal Add and Saturate
PHADDW Pq Qq ssse3 0F 38 01 r C2+ simdint Packed Horizontal Add
PHADDW Vdq Wdq ssse3 66 0F 38 01 r C2+ simdint Packed Horizontal Add
PHMINPOSUW Vdq Wdq sse41 66 0F 38 41 r C2++ D32 simdint compar Packed Horizontal Word Minimum
PHSUBD Pq Qq ssse3 0F 38 06 r C2+ simdint Packed Horizontal Subtract
PHSUBD Vdq Wdq ssse3 66 0F 38 06 r C2+ simdint Packed Horizontal Subtract
PHSUBSW Pq Qq ssse3 0F 38 07 r C2+ simdint Packed Horizontal Subtract and Saturate
PHSUBSW Vdq Wdq ssse3 66 0F 38 07 r C2+ simdint Packed Horizontal Subtract and Saturate
PHSUBW Pq Qq ssse3 0F 38 05 r C2+ simdint Packed Horizontal Subtract
PHSUBW Vdq Wdq ssse3 66 0F 38 05 r C2+ simdint Packed Horizontal Subtract
PINSRB Vdq Mb Ib sse41 66 0F 3A 20 r C2++ D32 simdint datamov Insert Byte
PINSRB Vdq Rd Ib
PINSRD Vdq Ed Ib sse41 66 0F 3A 22 r C2++ D32 simdint datamov Insert Dword/Qword
PINSRQ Vdq Eqp Ib
PINSRW Pq Rd Ib sse1 0F C4 r P3+ simdint Insert Word
PINSRW Pq Mw Ib
PINSRW Vdq Rd Ib sse1 66 0F C4 r P3+ simdint Insert Word
PINSRW Vdq Mw Ib
PMADDUBSW Pq Qq ssse3 0F 38 04 r C2+ simdint Multiply and Add Packed Signed and Unsigned Bytes
PMADDUBSW Vdq Wdq ssse3 66 0F 38 04 r C2+ simdint Multiply and Add Packed Signed and Unsigned Bytes
PMADDWD Pq Qd mmx 0F F5 r PX+ arith Multiply and Add Packed Integers
PMADDWD Vdq Wdq sse2 66 0F F5 r P4+ simdint arith Multiply and Add Packed Integers
PMAXSB Vdq Wdq sse41 66 0F 38 3C r C2++ D32 simdint compar Maximum of Packed Signed Byte Integers
PMAXSD Vdq Wdq sse41 66 0F 38 3D r C2++ D32 simdint compar Maximum of Packed Signed Dword Integers
PMAXSW Pq Qq sse1 0F EE r P3+ simdint Maximum of Packed Signed Word Integers
PMAXSW Vdq Wdq sse1 66 0F EE r P3+ simdint Maximum of Packed Signed Word Integers
PMAXUB Pq Qq sse1 0F DE r P3+ simdint Maximum of Packed Unsigned Byte Integers
PMAXUB Vdq Wdq sse1 66 0F DE r P3+ simdint Maximum of Packed Unsigned Byte Integers
PMAXUD Vdq Wdq sse41 66 0F 38 3F r C2++ D32 simdint compar Maximum of Packed Unsigned Dword Integers
PMAXUW Vdq Wdq sse41 66 0F 38 3E r C2++ D32 simdint compar Maximum of Packed Unsigned Word Integers
PMINSB Vdq Wdq sse41 66 0F 38 38 r C2++ D32 simdint compar Minimum of Packed Signed Byte Integers
PMINSD Vdq Wdq sse41 66 0F 38 39 r C2++ D32 simdint compar Minimum of Packed Signed Dword Integers
PMINSW Pq Qq sse1 0F EA r P3+ simdint Minimum of Packed Signed Word Integers
PMINSW Vdq Wdq sse1 66 0F EA r P3+ simdint Minimum of Packed Signed Word Integers
PMINUB Pq Qq sse1 0F DA r P3+ simdint Minimum of Packed Unsigned Byte Integers
PMINUB Vdq Wdq sse1 66 0F DA r P3+ simdint Minimum of Packed Unsigned Byte Integers
PMINUD Vdq Wdq sse41 66 0F 38 3B r C2++ D32 simdint compar Minimum of Packed Unsigned Dword Integers
PMINUW Vdq Wdq sse41 66 0F 38 3A r C2++ D32 simdint compar Minimum of Packed Unsigned Word Integers
PMOVMSKB Gd Nq sse1 0F D7 r P3+ simdint Move Byte Mask
PMOVMSKB Gd Udq sse1 66 0F D7 r P3+ simdint Move Byte Mask
PMOVSXBD Vdq Md sse41 66 0F 38 21 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXBD Vdq Udq
PMOVSXBQ Vdq Mw sse41 66 0F 38 22 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXBQ Vdq Udq
PMOVSXBW Vdq Mq sse41 66 0F 38 20 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXBW Vdq Udq
PMOVSXDQ Vdq Mq sse41 66 0F 38 25 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXDQ Vdq Udq
PMOVSXWD Vdq Mq sse41 66 0F 38 23 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXWD Vdq Udq
PMOVSXWQ Vdq Md sse41 66 0F 38 24 r C2++ D32 simdint conver Packed Move with Sign Extend
PMOVSXWQ Vdq Udq
PMOVZXBD Vdq Md sse41 66 0F 38 31 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXBD Vdq Udq
PMOVZXBQ Vdq Mw sse41 66 0F 38 32 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXBQ Vdq Udq
PMOVZXBW Vdq Mq sse41 66 0F 38 30 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXBW Vdq Udq
PMOVZXDQ Vdq Mq sse41 66 0F 38 35 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXDQ Vdq Udq
PMOVZXWD Vdq Mq sse41 66 0F 38 33 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXWD Vdq Udq
PMOVZXWQ Vdq Md sse41 66 0F 38 34 r C2++ D32 simdint conver Packed Move with Zero Extend
PMOVZXWQ Vdq Udq
PMULDQ Vdq Wdq sse41 66 0F 38 28 r C2++ D32 simdint arith Multiply Packed Signed Dword Integers
PMULHRSW Pq Qq ssse3 0F 38 0B r C2+ simdint Packed Multiply High with Round and Scale
PMULHRSW Vdq Wdq ssse3 66 0F 38 0B r C2+ simdint Packed Multiply High with Round and Scale
PMULHUW Pq Qq sse1 0F E4 r P3+ simdint Multiply Packed Unsigned Integers and Store High Result
PMULHUW Vdq Wdq sse1 66 0F E4 r P3+ simdint Multiply Packed Unsigned Integers and Store High Result
PMULHW Pq Qq mmx 0F E5 r PX+ arith Multiply Packed Signed Integers and Store High Result
PMULHW Vdq Wdq sse2 66 0F E5 r P4+ simdint arith Multiply Packed Signed Integers and Store High Result
PMULLD Vdq Wdq sse41 66 0F 38 40 r C2++ D32 simdint arith Multiply Packed Signed Dword Integers and Store Low Result
PMULLW Pq Qq mmx 0F D5 r PX+ arith Multiply Packed Signed Integers and Store Low Result
PMULLW Vdq Wdq sse2 66 0F D5 r P4+ simdint arith Multiply Packed Signed Integers and Store Low Result
PMULUDQ Pq Qq sse2 0F F4 r P4+ simdint arith Multiply Packed Unsigned DW Integers
PMULUDQ Vdq Wdq sse2 66 0F F4 r P4+ simdint arith Multiply Packed Unsigned DW Integers
POP ES 07 sr gen stack segreg Pop a Value from the Stack
POP CS 0F sR 00 D1 gen stack segreg Pop a Value from the Stack
POP SS 17 Sr gen stack segreg Pop a Value from the Stack
POP DS 1F SR gen stack segreg Pop a Value from the Stack
POP Zv 58 +r gen stack Pop a Value from the Stack
POP Ev 8F W 0 gen stack Pop a Value from the Stack
POP FS 0F A1 Sre 03+ gen stack segreg Pop a Value from the Stack
POP GS 0F A9 SrE 03+ gen stack segreg Pop a Value from the Stack
POPA DI SI BP ... 61 01+ gen stack Pop All General-Purpose Registers
POPAD EDI ESI EBP ... 61 03+ gen stack Pop All General-Purpose Registers
POPCNT Gv Ev F3 0F B8 r C2++ gen bit o..szapc o..s.apc Bit Population Count
POPF Fwo 9D gen stack flgctrl Pop Stack into FLAGS Register
POPFD Fdo 9D 03+ gen stack flgctrl Pop Stack into eFLAGS Register
POR Pq Qq mmx 0F EB r PX+ logical Bitwise Logical OR
POR Vdq Wdq sse2 66 0F EB r P4+ simdint logical Bitwise Logical OR
PREFETCHNTA Mb sse1 0F 18 0 P3+ fetch Prefetch Data Into Caches
PREFETCHT0 Mb sse1 0F 18 1 P3+ fetch Prefetch Data Into Caches
PREFETCHT1 Mb sse1 0F 18 2 P3+ fetch Prefetch Data Into Caches
PREFETCHT2 Mb sse1 0F 18 3 P3+ fetch Prefetch Data Into Caches
PSADBW Pq Qq sse1 0F F6 r P3+ simdint Compute Sum of Absolute Differences
PSADBW Vdq Wdq sse1 66 0F F6 r P3+ simdint Compute Sum of Absolute Differences
PSHUFB Pq Qq ssse3 0F 38 00 r C2+ simdint Packed Shuffle Bytes
PSHUFB Vdq Wdq ssse3 66 0F 38 00 r C2+ simdint Packed Shuffle Bytes
PSHUFD Vdq Wdq Ib sse2 66 0F 70 r P4+ simdint shunpck Shuffle Packed Doublewords
PSHUFHW Vdq Wdq Ib sse2 F3 0F 70 r P4+ simdint shunpck Shuffle Packed High Words
PSHUFLW Vdq Wdq Ib sse2 F2 0F 70 r P4+ simdint shunpck Shuffle Packed Low Words
PSHUFW Pq Qq Ib sse1 0F 70 r P3+ simdint Shuffle Packed Words
PSIGNB Pq Qq ssse3 0F 38 08 r C2+ simdint Packed SIGN
PSIGNB Vdq Wdq ssse3 66 0F 38 08 r C2+ simdint Packed SIGN
PSIGND Pq Qq ssse3 0F 38 0A r C2+ simdint Packed SIGN
PSIGND Vdq Wdq ssse3 66 0F 38 0A r C2+ simdint Packed SIGN
PSIGNW Pq Qq ssse3 0F 38 09 r C2+ simdint Packed SIGN
PSIGNW Vdq Wdq ssse3 66 0F 38 09 r C2+ simdint Packed SIGN
PSLLD Nq Ib mmx 0F 72 6 PX+ shift Shift Packed Data Left Logical
PSLLD Udq Ib sse2 66 0F 72 6 P4+ shift Shift Packed Data Left Logical
PSLLD Pq Qq mmx 0F F2 r PX+ shift Shift Packed Data Left Logical
PSLLD Vdq Wdq sse2 66 0F F2 r P4+ simdint shift Shift Packed Data Left Logical
PSLLDQ Udq Ib sse2 66 0F 73 7 P4+ simdint shift Shift Double Quadword Left Logical
PSLLQ Nq Ib mmx 0F 73 6 PX+ shift Shift Packed Data Left Logical
PSLLQ Udq Ib sse2 66 0F 73 6 P4+ shift Shift Packed Data Left Logical
PSLLQ Pq Qq mmx 0F F3 r PX+ shift Shift Packed Data Left Logical
PSLLQ Vdq Wdq sse2 66 0F F3 r P4+ simdint shift Shift Packed Data Left Logical
PSLLW Nq Ib mmx 0F 71 6 PX+ shift Shift Packed Data Left Logical
PSLLW Udq Ib sse2 66 0F 71 6 P4+ shift Shift Packed Data Left Logical
PSLLW Pq Qq mmx 0F F1 r PX+ shift Shift Packed Data Left Logical
PSLLW Vdq Wdq sse2 66 0F F1 r P4+ simdint shift Shift Packed Data Left Logical
PSRAD Nq Ib mmx 0F 72 4 PX+ shift Shift Packed Data Right Arithmetic
PSRAD Udq Ib sse2 66 0F 72 4 P4+ shift Shift Packed Data Right Arithmetic
PSRAD Pq Qq mmx 0F E2 r PX+ shift Shift Packed Data Right Arithmetic
PSRAD Vdq Wdq sse2 66 0F E2 r P4+ simdint shift Shift Packed Data Right Arithmetic
PSRAW Nq Ib mmx 0F 71 4 PX+ shift Shift Packed Data Right Arithmetic
PSRAW Udq Ib sse2 66 0F 71 4 P4+ shift Shift Packed Data Right Arithmetic
PSRAW Pq Qq mmx 0F E1 r PX+ shift Shift Packed Data Right Arithmetic
PSRAW Vdq Wdq sse2 66 0F E1 r P4+ simdint shift Shift Packed Data Right Arithmetic
PSRLD Nq Ib mmx 0F 72 2 PX+ shift Shift Double Quadword Right Logical
PSRLD Udq Ib sse2 66 0F 72 2 P4+ shift Shift Double Quadword Right Logical
PSRLD Pq Qq mmx 0F D2 r PX+ shift Shift Packed Data Right Logical
PSRLD Vdq Wdq sse2 66 0F D2 r P4+ simdint shift Shift Packed Data Right Logical
PSRLDQ Udq Ib sse2 66 0F 73 3 P4+ simdint shift Shift Double Quadword Right Logical
PSRLQ Nq Ib mmx 0F 73 2 PX+ shift Shift Packed Data Right Logical
PSRLQ Udq Ib sse2 66 0F 73 2 P4+ shift Shift Packed Data Right Logical
PSRLQ Pq Qq mmx 0F D3 r PX+ shift Shift Packed Data Right Logical
PSRLQ Vdq Wdq sse2 66 0F D3 r P4+ simdint shift Shift Packed Data Right Logical
PSRLW Nq Ib mmx 0F 71 2 PX+ shift Shift Packed Data Right Logical
PSRLW Udq Ib sse2 66 0F 71 2 P4+ shift Shift Packed Data Right Logical
PSRLW Pq Qq mmx 0F D1 r PX+ shift Shift Packed Data Right Logical
PSRLW Vdq Wdq sse2 66 0F D1 r P4+ simdint shift Shift Packed Data Right Logical
PSUBB Pq Qq mmx 0F F8 r PX+ arith Subtract Packed Integers
PSUBB Vdq Wdq sse2 66 0F F8 r P4+ simdint arith Subtract Packed Integers
PSUBD Pq Qq mmx 0F FA r PX+ arith Subtract Packed Integers
PSUBD Vdq Wdq sse2 66 0F FA r P4+ simdint arith Subtract Packed Integers
PSUBQ Pq Qq sse2 0F FB r P4+ simdint arith Subtract Packed Quadword Integers
PSUBQ Vdq Wdq sse2 66 0F FB r P4+ simdint arith Subtract Packed Quadword Integers
PSUBSB Pq Qq mmx 0F E8 r PX+ arith Subtract Packed Signed Integers with Signed Saturation
PSUBSB Vdq Wdq sse2 66 0F E8 r P4+ simdint arith Subtract Packed Signed Integers with Signed Saturation
PSUBSW Pq Qq mmx 0F E9 r PX+ arith Subtract Packed Signed Integers with Signed Saturation
PSUBSW Vdq Wdq sse2 66 0F E9 r P4+ simdint arith Subtract Packed Signed Integers with Signed Saturation
PSUBUSB Pq Qq mmx 0F D8 r PX+ arith Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSB Vdq Wdq sse2 66 0F D8 r P4+ simdint arith Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSW Pq Qq mmx 0F D9 r PX+ arith Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBUSW Vdq Wdq sse2 66 0F D9 r PX+ simdint arith Subtract Packed Unsigned Integers with Unsigned Saturation
PSUBW Pq Qq mmx 0F F9 r PX+ arith Subtract Packed Integers
PSUBW Vdq Wdq sse2 66 0F F9 r P4+ simdint arith Subtract Packed Integers
PTEST Vdq Wdq sse41 66 0F 38 17 r C2++ D32 o..szapc o..szapc o..s.ap. Logical Compare
PUNPCKHBW Pq Qq mmx 0F 68 r PX+ unpack Unpack High Data
PUNPCKHBW Vdq Wdq sse2 66 0F 68 r P4+ simdint shunpck Unpack High Data
PUNPCKHDQ Pq Qq mmx 0F 6A r PX+ unpack Unpack High Data
PUNPCKHDQ Vdq Wdq sse2 66 0F 6A r P4+ simdint shunpck Unpack High Data
PUNPCKHQDQ Vdq Wdq sse2 66 0F 6D r P4+ simdint shunpck Unpack High Data
PUNPCKHWD Pq Qq mmx 0F 69 r PX+ unpack Unpack High Data
PUNPCKHWD Vdq Wdq sse2 66 0F 69 r P4+ simdint shunpck Unpack High Data
PUNPCKLBW Pq Qd mmx 0F 60 r PX+ unpack Unpack Low Data
PUNPCKLBW Vdq Wdq sse2 66 0F 60 r P4+ simdint shunpck Unpack Low Data
PUNPCKLDQ Pq Qd mmx 0F 62 r PX+ unpack Unpack Low Data
PUNPCKLDQ Vdq Wdq sse2 66 0F 62 r P4+ simdint shunpck Unpack Low Data
PUNPCKLQDQ Vdq Wdq sse2 66 0F 6C r P4+ simdint shunpck Unpack Low Data
PUNPCKLWD Pq Qd mmx 0F 61 r PX+ unpack Unpack Low Data
PUNPCKLWD Vdq Wdq sse2 66 0F 61 r P4+ simdint shunpck Unpack Low Data
PUSH ES 06 sr gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSH CS 0E sR gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSH SS 16 Sr gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSH DS 1E SR gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSH Zv 50 +r gen stack Push Word, Doubleword or Quadword Onto the Stack
PUSH Ivs 68 01+ gen stack Push Word, Doubleword or Quadword Onto the Stack
PUSH Ibss 6A S 01+ gen stack Push Word, Doubleword or Quadword Onto the Stack
PUSH Ev FF 6 gen stack Push Word, Doubleword or Quadword Onto the Stack
PUSH FS 0F A0 Sre 03+ gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSH GS 0F A8 SrE 03+ gen stack segreg Push Word, Doubleword or Quadword Onto the Stack
PUSHA AX CX DX ... 60 01+ gen stack Push All General-Purpose Registers
PUSHAD EAX ECX EDX ... 60 03+ gen stack Push All General-Purpose Registers
PUSHF Fwo 9C gen stack flgctrl Push FLAGS Register onto the Stack
PUSHFD Fdo 9C 03+ gen stack flgctrl Push eFLAGS Register onto the Stack
PXOR Pq Qq mmx 0F EF r PX+ logical Logical Exclusive OR
PXOR Vdq Wdq sse2 66 0F EF r P4+ simdint logical Logical Exclusive OR
RCL Eb Ib C0 w 2 01+ gen shftrot .......c o..szapc o..szapc o....... Rotate
RCL Ev Ib C1 W 2 01+ gen shftrot .......c o..szapc o..szapc o....... Rotate
RCL Eb 1 D0 w 2 gen shftrot .......c o..szapc o..szapc Rotate
RCL Ev 1 D1 W 2 gen shftrot .......c o..szapc o..szapc Rotate
RCL Eb CL D2 w 2 gen shftrot .......c o..szapc o..szapc o....... Rotate
RCL Ev CL D3 W 2 gen shftrot .......c o..szapc o..szapc o....... Rotate
RCPPS Vps Wps sse1 0F 53 r P3+ simdfp arith Compute Reciprocals of Packed Single-FP Values
RCPSS Vss Wss sse1 F3 0F 53 r P3+ simdfp arith Compute Reciprocal of Scalar Single-FP Values
RCR Eb Ib C0 w 3 01+ gen shftrot .......c o..szapc o..szapc o....... Rotate
RCR Ev Ib C1 W 3 01+ gen shftrot .......c o..szapc o..szapc o....... Rotate
RCR Eb 1 D0 w 3 gen shftrot .......c o..szapc o..szapc Rotate
RCR Ev 1 D1 W 3 gen shftrot .......c o..szapc o..szapc Rotate
RCR Eb CL D2 w 3 gen shftrot .......c o..szapc o..szapc o....... Rotate
RCR Ev CL D3 W 3 gen shftrot .......c o..szapc o..szapc o....... Rotate
RDMSR EAX EDX ECX MSR 0F 32 P1+ 0 system Read from Model Specific Register
RDPMC EAX EDX PMC 0F 33 PX+ f3 system Read Performance-Monitoring Counters
RDTSC EAX EDX I... 0F 31 P1+ f2 system Read Time-Stamp Counter
RDTSCP EAX EDX ECX ... 0F 01 F9 7 C7+ f2 system Read Time-Stamp Counter and Processor ID
REP eCX F2 U17 prefix string Repeat String Operation Prefix
REP eCX F3 D17 prefix string Repeat String Operation Prefix
REPNZ eCX F2 D17 prefix string ....z... Repeat String Operation Prefix
REPNE eCX
REPZ eCX F3 D17 prefix string ....z... Repeat String Operation Prefix
REPE eCX
RETF Iw CA f gen branch stack Return from procedure
RETF CB f gen branch stack Return from procedure
RETN Iw C2 gen branch stack Return from procedure
RETN C3 gen branch stack Return from procedure
ROL Eb Ib C0 w 0 01+ gen shftrot o..szapc o..szapc o....... Rotate
ROL Ev Ib C1 W 0 01+ gen shftrot o..szapc o..szapc o....... Rotate
ROL Eb 1 D0 w 0 gen shftrot o..szapc o..szapc Rotate
ROL Ev 1 D1 W 0 gen shftrot o..szapc o..szapc Rotate
ROL Eb CL D2 w 0 gen shftrot o..szapc o..szapc o....... Rotate
ROL Ev CL D3 W 0 gen shftrot o..szapc o..szapc o....... Rotate
ROR Eb Ib C0 w 1 01+ gen shftrot o..szapc o..szapc o....... Rotate
ROR Ev Ib C1 W 1 01+ gen shftrot o..szapc o..szapc o....... Rotate
ROR Eb 1 D0 w 1 gen shftrot o..szapc o..szapc Rotate
ROR Ev 1 D1 W 1 gen shftrot o..szapc o..szapc Rotate
ROR Eb CL D2 w 1 gen shftrot o..szapc o..szapc o....... Rotate
ROR Ev CL D3 W 1 gen shftrot o..szapc o..szapc o....... Rotate
ROUNDPD Vps Wpd Ib sse41 66 0F 3A 09 r C2++ D32 simdfp conver Round Packed Double-FP Values
ROUNDPS Vps Wps Ib sse41 66 0F 3A 08 r C2++ D32 simdfp conver Round Packed Single-FP Values
ROUNDSD Vsd Wsd Ib sse41 66 0F 3A 0B r C2++ D32 simdfp conver Round Scalar Double-FP Values
ROUNDSS Vss Wss Ib sse41 66 0F 3A 0A r C2++ D32 simdfp conver Round Scalar Single-FP Values
RSM Fw 0F AA 03++ S system branch Resume from System Management Mode
RSQRTPS Vps Wps sse1 0F 52 r P3+ simdfp arith Compute Recipr. of Square Roots of Packed Single-FP Values
RSQRTSS Vss Wss sse1 F3 0F 52 r P3+ simdfp arith Compute Recipr. of Square Root of Scalar Single-FP Value
SAHF AH 9E gen datamov flgctrl ...szapc ...szapc Store AH into Flags
SAL alias Eb Ib C0 w 6 01+ U5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHL alias Eb Ib
SAL alias Ev Ib C1 W 6 01+ U5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHL alias Ev Ib
SAL alias Eb 1 D0 w 6 U5 gen shftrot o..szapc o..sz.pc .....a.. Shift
SHL alias Eb 1
SAL alias Ev 1 D1 W 6 U5 gen shftrot o..szapc o..sz.pc .....a.. Shift
SHL alias Ev 1
SAL alias Eb CL D2 w 6 U5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHL alias Eb CL
SAL alias Ev CL D3 W 6 U5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHL alias Ev CL
SALC AL D6 02+ U6 gen datamov .......c Set AL If Carry
SETALC AL
SAR Eb Ib C0 w 7 01+ gen shftrot o..szapc o..sz.pc o....a.. Shift
SAR Ev Ib C1 W 7 01+ gen shftrot o..szapc o..sz.pc o....a.. Shift
SAR Eb 1 D0 w 7 gen shftrot o..szapc o..sz.pc .....a.. Shift
SAR Ev 1 D1 W 7 gen shftrot o..szapc o..sz.pc .....a.. Shift
SAR Eb CL D2 w 7 gen shftrot o..szapc o..sz.pc o....a.. Shift
SAR Ev CL D3 W 7 gen shftrot o..szapc o..sz.pc .....a.. Shift
SBB Eb Gb 18 dw r L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Ev Gv 19 dW r L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Gb Eb 1A Dw r gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Gv Ev 1B DW r gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB AL Ib 1C w gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB eAX Iv 1D W gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Eb Ib 80 w 3 L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Ev Iv 81 W 3 L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB alias Eb Ib 82 w 3 L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SBB Ev Ibs 83 SW 3 L gen arith binary .......c o..szapc o..szapc Integer Subtraction with Borrow
SCAS Yb AL AE w gen arith string binary .d...... o..szapc o..szapc Scan String
SCASB Yb AL
SCAS Ywo AX AF W gen arith string binary .d...... o..szapc o..szapc Scan String
SCASW Ywo AX
SCAS Yv eAX AF W 03+ gen arith string binary .d...... o..szapc o..szapc Scan String
SCASD Ydo EAX
SETB Eb 0F 92 ttTn 0 03+ D25 gen datamov .......c Set Byte on Condition - below/not above or equal/carry (CF=1)
SETNAE Eb
SETC Eb
SETBE Eb 0F 96 tTTn 0 03+ D25 gen datamov ....z..c Set Byte on Condition - below or equal/not above (CF=1 OR ZF=1)
SETNA Eb
SETL Eb 0F 9C TTtn 0 03+ D25 gen datamov o..s.... Set Byte on Condition - less/not greater (SF!=OF)
SETNGE Eb
SETLE Eb 0F 9E TTTn 0 03+ D25 gen datamov o..sz... Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
SETNG Eb
SETNB Eb 0F 93 ttTN 0 03+ D25 gen datamov .......c Set Byte on Condition - not below/above or equal/not carry (CF=0)
SETAE Eb
SETNC Eb
SETNBE Eb 0F 97 tTTN 0 03+ D25 gen datamov ....z..c Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
SETA Eb
SETNL Eb 0F 9D TTtN 0 03+ D25 gen datamov o..s.... Set Byte on Condition - not less/greater or equal (SF=OF)
SETGE Eb
SETNLE Eb 0F 9F TTTN 0 03+ D25 gen datamov o..sz... Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
SETG Eb
SETNO Eb 0F 91 tttN 0 03+ D25 gen datamov o....... Set Byte on Condition - not overflow (OF=0)
SETNP Eb 0F 9B TtTN 0 03+ D25 gen datamov ......p. Set Byte on Condition - not parity/parity odd (PF=0)
SETPO Eb
SETNS Eb 0F 99 TttN 0 03+ D25 gen datamov ...s.... Set Byte on Condition - not sign (SF=0)
SETNZ Eb 0F 95 tTtN 0 03+ D25 gen datamov ....z... Set Byte on Condition - not zero/not equal (ZF=0)
SETNE Eb
SETO Eb 0F 90 tttn 0 03+ D25 gen datamov o....... Set Byte on Condition - overflow (OF=1)
SETP Eb 0F 9A TtTn 0 03+ D25 gen datamov ......p. Set Byte on Condition - parity/parity even (PF=1)
SETPE Eb
SETS Eb 0F 98 Tttn 0 03+ D25 gen datamov ...s.... Set Byte on Condition - sign (SF=1)
SETZ Eb 0F 94 tTtn 0 03+ D25 gen datamov ....z... Set Byte on Condition - zero/equal (ZF=1)
SETE Eb
SFENCE sse1 0F AE 7 P3+ order Store Fence
SGDT Ms GDTR 0F 01 0 02+ system Store Global Descriptor Table Register
SHL Eb Ib C0 w 4 01+ gen shftrot o..szapc o..sz.pc o....a.c Shift
SAL Eb Ib
SHL Ev Ib C1 W 4 01+ gen shftrot o..szapc o..sz.pc o....a.c Shift
SAL Ev Ib
SHL Eb 1 D0 w 4 gen shftrot o..szapc o..sz.pc .....a.. Shift
SAL Eb 1
SHL Ev 1 D1 W 4 gen shftrot o..szapc o..sz.pc .....a.. Shift
SAL Ev 1
SHL Eb CL D2 w 4 gen shftrot o..szapc o..sz.pc o....a.c Shift
SAL Eb CL
SHL Ev CL D3 W 4 gen shftrot o..szapc o..sz.pc o....a.c Shift
SAL Ev CL
SHLD Ev Gv Ib 0F A4 d r 03+ gen shftrot o..szapc o..sz.pc o....a.c Double Precision Shift Left
SHLD Ev Gv CL 0F A5 d r 03+ gen shftrot o..szapc o..sz.pc o....a.c Double Precision Shift Left
SHR Eb Ib C0 w 5 01+ gen shftrot o..szapc o..sz.pc o....a.c Shift
SHR Ev Ib C1 W 5 01+ gen shftrot o..szapc o..sz.pc o....a.c Shift
SHR Eb 1 D0 w 5 gen shftrot o..szapc o..sz.pc .....a.. Shift
SHR Ev 1 D1 W 5 gen shftrot o..szapc o..sz.pc .....a.. Shift
SHR Eb CL D2 w 5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHR Ev CL D3 W 5 gen shftrot o..szapc o..sz.pc o....a.c Shift
SHRD Ev Gv Ib 0F AC d r 03+ gen shftrot o..szapc o..sz.pc o....a.c Double Precision Shift Right
SHRD Ev Gv CL 0F AD d r 03+ gen shftrot o..szapc o..sz.pc o....a.c Double Precision Shift Right
SHUFPD Vpd Wpd Ib sse2 66 0F C6 r P4+ pcksclr shunpck Shuffle Packed Double-FP Values
SHUFPS Vps Wps Ib sse1 0F C6 r P3+ simdfp shunpck Shuffle Packed Single-FP Values
SIDT Ms IDTR 0F 01 1 02+ system Store Interrupt Descriptor Table Register
SLDT Mw LDTR 0F 00 0 02+ P system Store Local Descriptor Table Register
SLDT Rv LDTR
SMSW Mw MSW 0F 01 4 02+ D19 system Store Machine Status Word
SMSW Rv MSW
SQRTPD Vpd Wpd sse2 66 0F 51 r P4+ pcksclr arith Compute Square Roots of Packed Double-FP Values
SQRTPS Vps Wps sse1 0F 51 r P3+ simdfp arith Compute Square Roots of Packed Single-FP Values
SQRTSD Vsd Wsd sse2 F2 0F 51 r P4+ pcksclr arith Compute Square Root of Scalar Double-FP Value
SQRTSS Vss Wss sse1 F3 0F 51 r P3+ simdfp arith Compute Square Root of Scalar Single-FP Value
SS SS 36 prefix segreg SS segment override prefix
STC F9 gen flgctrl .......c .......c .......C Set Carry Flag
STD FD gen flgctrl .d...... .d...... .D...... Set Direction Flag
STI FB f1 gen flgctrl ..i..... ..i..... ..I..... Set Interrupt Flag
STMXCSR Md sse1 0F AE 3 P3+ mxcsrsm Store MXCSR Register State
STOS Yb AL AA w gen datamov string .d...... Store String
STOSB Yb AL
STOS Ywo AX AB W gen datamov string .d...... Store String
STOSW Ywo AX
STOS Yv eAX AB W 03+ gen datamov string .d...... Store String
STOSD Ydo EAX
STR Mw TR 0F 00 1 02+ P system Store Task Register
STR Rv TR
SUB Eb Gb 28 dw r L gen arith binary o..szapc o..szapc Subtract
SUB Ev Gv 29 dW r L gen arith binary o..szapc o..szapc Subtract
SUB Gb Eb 2A Dw r gen arith binary o..szapc o..szapc Subtract
SUB Gv Ev 2B DW r gen arith binary o..szapc o..szapc Subtract
SUB AL Ib 2C w gen arith binary o..szapc o..szapc Subtract
SUB eAX Iv 2D W gen arith binary o..szapc o..szapc Subtract
SUB Eb Ib 80 w 5 L gen arith binary o..szapc o..szapc Subtract
SUB Ev Iv 81 W 5 L gen arith binary o..szapc o..szapc Subtract
SUB alias Eb Ib 82 w 5 L gen arith binary o..szapc o..szapc Subtract
SUB Ev Ibs 83 SW 5 L gen arith binary o..szapc o..szapc Subtract
SUBPD Vpd Wpd sse2 66 0F 5C r P4+ pcksclr arith Subtract Packed Double-FP Values
SUBPS Vps Wps sse1 0F 5C r P3+ simdfp arith Subtract Packed Single-FP Values
SUBSD Vsd Wsd sse2 F2 0F 5C r P4+ pcksclr arith Subtract Scalar Double-FP Values
SUBSS Vss Wss sse1 F3 0F 5C r P3+ simdfp arith Subtract Scalar Single-FP Values
SYSENTER SS ESP I... ... 0F 34 Sr P2+ P system branch ..i..... ..i..... ..i..... Fast System Call
SYSEXIT SS eSP I... ... 0F 35 Sr P2+ P 0 system branch trans Fast Return from Fast System Call
TAKEN 3E P4 D2 prefix branch cond Branch taken prefix (only with Jcc instructions)
TEST Eb Gb 84 dw r gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST Ev Gv 85 dW r gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST AL Ib A8 w gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST eAX Iv A9 W gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST Eb Ib F6 w 0 gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST alias Eb Ib F6 w 1 U18 gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST Ev Iv F7 W 0 gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
TEST alias Ev Iv F7 W 1 U18 gen logical o..szapc o..sz.pc .....a.. o......c Logical Compare
UCOMISD Vsd Wsd sse2 66 0F 2E r P4+ pcksclr compar ....z.pc ....z.pc Unordered Compare Scalar Double-FP Values and Set EFLAGS
UCOMISS Vss Wss sse1 0F 2E r P3+ simdfp compar ....z.pc ....z.pc Unordered Compare Scalar Single-FP Values and Set EFLAGS
UD G E 0F B9 r 02+ M27 gen control Undefined Instruction
UD2 0F 0B 02+ gen control Undefined Instruction
UNPCKHPD Vpd Wpd sse2 66 0F 15 r P4+ pcksclr shunpck Unpack and Interleave High Packed Double-FP Values
UNPCKHPS Vps Wq sse1 0F 15 r P3+ simdfp shunpck Unpack and Interleave High Packed Single-FP Values
UNPCKLPD Vpd Wpd sse2 66 0F 14 r P4+ pcksclr shunpck Unpack and Interleave Low Packed Double-FP Values
UNPCKLPS Vps Wq sse1 0F 14 r P3+ simdfp shunpck Unpack and Interleave Low Packed Single-FP Values
VERR Ew 0F 00 4 02+ P system ....z... ....z... Verify a Segment for Reading
VERW Ew 0F 00 5 02+ P system ....z... ....z... Verify a Segment for Writing
VMCALL vmx 0F 01 C1 0 P4++ D31 P 0 o..szapc o..szapc Call to VM Monitor
VMCLEAR Mq vmx 66 0F C7 6 P4++ D31 P 0 o..szapc o..szapc Clear Virtual-Machine Control Structure
VMLAUNCH vmx 0F 01 C2 0 P4++ D31 P 0 o..szapc o..szapc Launch Virtual Machine
VMPTRLD Mq vmx 0F C7 6 P4++ D31 P 0 o..szapc o..szapc Load Pointer to Virtual-Machine Control Structure
VMPTRST Mq vmx 0F C7 7 P4++ D31 P 0 o..szapc o..szapc Store Pointer to Virtual-Machine Control Structure
VMREAD Ed Gd vmx 0F 78 r P4++ D31 P 0 o..szapc o..szapc Read Field from Virtual-Machine Control Structure
VMRESUME vmx 0F 01 C3 0 P4++ D31 P 0 o..szapc o..szapc Resume Virtual Machine
VMWRITE Gd Ed vmx 0F 79 r P4++ D31 P 0 o..szapc o..szapc Write Field to Virtual-Machine Control Structure
VMXOFF vmx 0F 01 C4 0 P4++ D31 P 0 o..szapc o..szapc Leave VMX Operation
VMXON Mq vmx F3 0F C7 6 P4++ D31 P 0 o..szapc o..szapc Enter VMX Operation
WBINVD 0F 09 04+ 0 system Write Back and Invalidate Cache
WRMSR MSR ECX EAX EDX 0F 30 P1+ 0 system Write to Model Specific Register
XADD Eb Gb 0F C0 dw r 04+ L gen datamov arith binary o..szapc o..szapc Exchange and Add
XADD Ev Gv 0F C1 dW r 04+ L gen datamov arith binary o..szapc o..szapc Exchange and Add
XCHG Gb Eb 86 Dw r L gen datamov Exchange Register/Memory with Register
XCHG Gv Ev 87 DW r L gen datamov Exchange Register/Memory with Register
XCHG Zv eAX 90 +r gen datamov Exchange Register/Memory with Register
XGETBV EDX EAX ECX XCR 0F 01 D0 2 C2++ system Get Value of Extended Control Register
XLAT AL BBb D7 gen datamov Table Look-up Translation
XLATB AL BBb
XOR Eb Gb 30 dw r L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Ev Gv 31 dW r L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Gb Eb 32 Dw r gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Gv Ev 33 DW r gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR AL Ib 34 w gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR eAX Iv 35 W gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Eb Ib 80 w 6 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Ev Iv 81 W 6 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR alias Eb Ib 82 w 6 L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XOR Ev Ibs 83 SW 6 03+ L gen logical o..szapc o..sz.pc .....a.. o......c Logical Exclusive OR
XORPD Vpd Wpd sse2 66 0F 57 r P4+ pcksclr logical Bitwise Logical XOR for Double-FP Values
XORPS Vps Wps sse1 0F 57 r P3+ simdfp logical Bitwise Logical XOR for Single-FP Values
XRSTOR ST ST1 ST2 ... 0F AE 5 C2++ system Restore Processor Extended States
XSAVE M EDX EAX ... 0F AE 4 C2++ system Save Processor Extended States
XSETBV XCR ECX EDX EAX 0F 01 D1 2 C2++ 0 system Set Extended Control Register

Printing is not enabled. You can order a printed copy in the store, or get access to benefits, which include also printable HTML and PDF files.

General notes:

  1. POP CS
    1. Intel iAPX 86/88, 186/188 User's manual: When the opcode 0FH is encountered, the 8086,88 will execute a POP CS; the 80186,188 will execute an illegal instruction exception.
  2. Branch Prefixes
    1. Branch hints have effect only on NetBurst microarchitecture: A Detailed Look Inside the Intel NetBurst Micro-Architecture of the Intel Pentium 4 Processor: Branch hints are interpreted by the translation engine, and are used to assist branch prediction and trace construction hardware. They are only used at trace build time, and have no effect within already-built traces.
    2. Alternating branch prefix: The microarchitecture of Intel and AMD CPU's, By Agner Fog, Copyright © 1996 - 2006.
  3. 90 NOP
    1. 90 NOP is not really aliased to XCHG eAX, eAX instruction. This is important in 64-bit mode where the implicit zero-extension to RAX does not happen
  4. F390 opcode
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, PAUSE instruction
  5. SAL
    1. sandpile.org -- IA-32 architecture -- opcode groups
  6. SALC
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
  7. FSTP aliases
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (D9 /3, mod = 11b, DF /2, mod = 11b, DF /3, mod = 11b) in the instruction stream, it will execute it as follows: FSTP ST(i)
  8. FSTP1
    1. Christian Ludloff wrote: While FSTP (D9 /3, mod < 11b), FSTP8 (DF /2, mod = 11b), and FSTP9 (DF /3, mod = 11b) do signal stack underflow, FSTP1 (D9 /3, mod = 11b) does not.
  9. FNENI and FNDISI
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Processor Control Instructions: The 8087 instructions FENI and FDISI perform no function in the 80287. If these opcodes are detected in an 80286/80287 instruction stream, the 80287 will perform no specific operation and no internal states will be affected.
  10. FNSETPM
    1. INTEL 80387 PROGRAMMER'S REFERENCE MANUAL 1987, 6.1.2 Independent of CPU Addressing Modes: Unlike the 80287, the 80387 is not sensitive to the addressing and memory management of the CPU. The 80387 operates the same regardless of whether the 80386 CPU is operating in real-address mode, in protected mode, or in virtual 8086 mode.
  11. FCOM alias
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOM ST(i)
  12. FCOMP aliases
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DC /3, mod = 11b, DE /2, mod = 11b) in the instruction stream, it will execute it as follows: FCOMP ST(i)
  13. FXCH aliases
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DD /1, mod = 11b, DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FXCH ST(i)
  14. FFREEP
    1. INTEL 80287 PROGRAMMER'S REFERENCE MANUAL 1987, Table A-2. Machine Instruction Decoding Guide: If the 80287 encounters one of these encodings (DF /1, mod = 11b) in the instruction stream, it will execute it as follows: FFREE ST(i) and pop stack
    2. Intel Architecture Optimization Reference Manual PIII, Table C-1 Pentium II and Pentium III Processors Instruction to Decoder Specification
    3. AMD Athlon Processor x86 Code Optimization Guide, Chapter 9, Use FFREEP Macro to Pop One Register from the FPU Stack
    4. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  15. X87 aliases
    1. sandpile.org -- IA-32 architecture -- ESC (FP) opcodes
  16. INT1, ICEBP
    1. sandpile.org -- IA-32 architecture -- one byte opcodes
    2. AMD64 Architecture Programmer's Manual Volume 3, Table One-Bytes Opcodes
    3. Christian Ludloff wrote: Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB.
  17. REP prefixes
    1. Flags aren't updated until after the last iteration to make the operation faster
  18. TEST
    1. sandpile.org -- IA-32 architecture -- opcode groups
    2. Christian Ludloff wrote: While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it.
    3. AMD64 Architecture Programmer's Manual Volume 3, Table One-Byte and Two-Byte Opcode ModRM Extensions
  19. SMSW r32/64
    1. Some processors support reading whole CR0 register, causing a security flaw.
  20. LOADALL
    1. sandpile.org -- IA-32 architecture -- two byte opcodes
    2. www.x86.org - The LOADALL Instruction
  21. 0F0D NOP
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. AMD architecture maps 3DNow! PREFETCH instructions here
  22. Hintable NOP
    1. See U.S. Patent 5,701,442
    2. sandpile.org -- IA-32 architecture -- opcode groups
  23. MOV from/to CRn, DRn, TRn
    1. Christian Ludloff wrote: For the MOVs from/to CRx/DRx/TRx, mod=00b/01b/10b is aliased to 11b.
    2. AMD64 Architecture Programmer's Manual Volume 3, System Instruction Reference: This instruction is always treated as a register-to-register instruction, regardless of the encoding of the MOD field in the MODR/M byte.
  24. GETSEC Leaf Functions
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z: The GETSEC instruction supports multiple leaf functions. Leaf functions are selected by the value in EAX at the time GETSEC is executed. The following leaf functions are available: CAPABILITIES, ENTERACCS, EXITAC, SENTER, SEXIT, PARAMETERS, SMCTRL, WAKEUP. GETSEC instruction operands are specific to selected leaf function.
  25. SETcc
    1. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The reg field in the ModR/M byte is unused.
  26. CMPXCHG with memory operand
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: CMPXCHG always does a read-modify-write on the memory operand.
  27. 0FB9 UD
    1. Intel 64 and IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z, Two-byte Opcode Map
    2. sandpile.org -- IA-32 architecture -- two byte opcodes
  28. CMPXCHG8B, CMPXCHG16B
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction can be used with a LOCK prefix …. To simplify the interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the comparison.
    2. AMD64 Architecture Programmers Manual Volume 3: General-Purpose and System Instructions: The CMPXCHG8B and CMPXCHG16B instructions always do a read-modify-write on the memory operand.
    3. CMPXCHG16B is invalid on early steppings of AMD64 architecture.
  29. BSWAP r16
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: When the BSWAP instruction references a 16-bit register, the result is undefined.
    2. AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions: The result of applying the BSWAP instruction to a 16-bit register is undefined.
  30. MASKMOVQ
    1. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M: This instruction causes a transition from x87 FPU to MMX technology state.
  31. Intel VMX
    1. Intel VMX is not binary-compatible with AMD SVM
  32. Intel SSE4
    1. AMD64 architecture does not support SSE4 instructions but PTEST as part of SSE5

Notes for the Ring Level, used in case of f mark:

  1. rFlags.IOPL
  2. CR4.TSD[bit 2]
  3. CR4.PCE[bit 8]

Create a hypertext reference to this edition's mnemonic group (append mnemonic's starting letter at the end of the following line):

http://ref.x86asm.net/geek32-abc.html#

32-bit ModR/M Byte

r8(/r) AL CL DL BL AH CH DH BH
r16(/r) AX CX DX BX SP BP SI DI
r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI
mm(/r) MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7
xmm(/r) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
sreg ES CS SS DS FS GS res. res.
eee CR0 invd CR2 CR3 CR4 invd invd invd
eee DR0 DR1 DR2 DR3 DR41 DR51 DR6 DR7
(In decimal) /digit (Opcode) 0 1 2 3 4 5 6 7
(In binary) REG = 000 001 010 011 100 101 110 111
Effective Address Mod R/M Value of ModR/M Byte (in Hex)
[EAX] 00 000 00 08 10 18 20 28 30 38
[ECX] 001 01 09 11 19 21 29 31 39
[EDX] 010 02 0A 12 1A 22 2A 32 3A
[EBX] 011 03 0B 13 1B 23 2B 33 3B
[sib] 100 04 0C 14 1C 24 2C 34 3C
disp32 101 05 0D 15 1D 25 2D 35 3D
[ESI] 110 06 0E 16 1E 26 2E 36 3E
[EDI] 111 07 0F 17 1F 27 2F 37 3F
[EAX]+disp8 01 000 40 48 50 58 60 68 70 78
[ECX]+disp8 001 41 49 51 59 61 69 71 79
[EDX]+disp8 010 42 4A 52 5A 62 6A 72 7A
[EBX]+disp8 011 43 4B 53 5B 63 6B 73 7B
[sib]+disp8 100 44 4C 54 5C 64 6C 74 7C
[EBP]+disp8 101 45 4D 55 5D 65 6D 75 7D
[ESI]+disp8 110 46 4E 56 5E 66 6E 76 7E
[EDI]+disp8 111 47 4F 57 5F 67 6F 77 7F
[EAX]+disp32 10 000 80 88 90 98 A0 A8 B0 B8
[ECX]+disp32 001 81 89 91 99 A1 A9 B1 B9
[EDX]+disp32 010 82 8A 92 9A A2 AA B2 BA
[EBX]+disp32 011 83 8B 93 9B A3 AB B3 BB
[sib]+disp32 100 84 8C 94 9C A4 AC B4 BC
[EBP]+disp32 101 85 8D 95 9D A5 AD B5 BD
[ESI]+disp32 110 86 8E 96 9E A6 AE B6 BE
[EDI]+disp32 111 87 8F 97 9F A7 AF B7 BF
AL/AX/EAX/ST0/MM0/XMM0 11 000 C0 C8 D0 D8 E0 E8 F0 F8
CL/CX/ECX/ST1/MM1/XMM1 001 C1 C9 D1 D9 E1 E9 F1 F9
DL/DX/EDX/ST2/MM2/XMM2 010 C2 CA D2 DA E2 EA F2 FA
BL/BX/EBX/ST3/MM3/XMM3 011 C3 CB D3 DB E3 EB F3 FB
AH/SP/ESP/ST4/MM4/XMM4 100 C4 CC D4 DC E4 EC F4 FC
CH/BP/EBP/ST5/MM5/XMM5 101 C5 CD D5 DD E5 ED F5 FD
DH/SI/ESI/ST6/MM6/XMM6 110 C6 CE D6 DE E6 EE F6 FE
BH/DI/EDI/ST7/MM7/XMM7 111 C7 CF D7 DF E7 EF F7 FF

32-bit SIB Byte

r32 EAX ECX EDX EBX ESP →1 ESI EDI
(In decimal) Base = 0 1 2 3 4 5 6 7
(In binary) Base = 000 001 010 011 100 101 110 111
Scaled Index SS Index Value of SIB Byte (in Hexadecimal)
[EAX] 00 000 00 01 02 03 04 05 06 07
[ECX] 001 08 09 0A 0B 0C 0D 0E 0F
[EDX] 010 10 11 12 13 14 15 16 17
[EBX] 011 18 19 1A 1B 1C 1D 1E 1F
none 100 20 21 22 23 24 25 26 27
[EBP] 101 28 29 2A 2B 2C 2D 2E 2F
[ESI] 110 30 31 32 33 34 35 36 37
[EDI] 111 38 39 3A 3B 3C 3D 3E 3F
[EAX*2] 01 000 40 41 42 43 44 45 46 47
[ECX*2] 001 48 49 4A 4B 4C 4D 4E 4F
[EDX*2] 010 50 51 52 53 54 55 56 57
[EBX*2] 011 58 59 5A 5B 5C 5D 5E 5F
none 100 60 61 62 63 64 65 66 67
[EBP*2] 101 68 69 6A 6B 6C 6D 6E 6F
[ESI*2] 110 70 71 72 73 74 75 76 77
[EDI*2] 111 78 79 7A 7B 7C 7D 7E 7F
[EAX*4] 10 000 80 81 82 83 84 85 86 87
[ECX*4] 001 88 89 8A 8B 8C 8D 8E 8F
[EDX*4] 010 90 91 92 93 94 95 96 97
[EBX*4] 011 98 99 9A 9B 9C 9D 9E 9F
none 100 A0 A1 A2 A3 A4 A5 A6 A7
[EBP*4] 101 A8 A9 AA AB AC AD AE AF
[ESI*4] 110 B0 B1 B2 B3 B4 B5 B6 B7
[EDI*4] 111 B8 B9 BA BB BC BD BE BF
[EAX*8] 11 000 C0 C1 C2 C3 C4 C5 C6 C7
[ECX*8] 001 C8 C9 CA CB CC CD CE CF
[EDX*8] 010 D0 D1 D2 D3 D4 D5 D6 D7
[EBX*8] 011 D8 D9 DA DB DC DD DE DF
none 100 E0 E1 E2 E3 E4 E5 E6 E7
[EBP*8] 101 E8 E9 EA EB EC ED EE EF
[ESI*8] 110 F0 F1 F2 F3 F4 F5 F6 F7
[EDI*8] 111 F8 F9 FA FB FC FD FE FF
SIB Note 1
Mod bits base
00 disp32
01 EBP+disp8
10 EBP+disp32

16-bit ModR/M Byte

r8(/r) AL CL DL BL AH CH DH BH
r16(/r) AX CX DX BX SP BP SI DI
r32(/r) EAX ECX EDX EBX ESP EBP ESI EDI
mm(/r) MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7
xmm(/r) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
sreg ES CS SS DS FS GS res. res.
eee CR0 invd CR2 CR3 CR4 invd invd invd
eee DR0 DR1 DR2 DR3 DR41 DR51 DR6 DR7
(In decimal) /digit (Opcode) 0 1 2 3 4 5 6 7
(In binary) REG = 000 001 010 011 100 101 110 111
Effective Address Mod R/M Value of ModR/M Byte (in Hex)
[BX+SI] 00 000 00 08 10 18 20 28 30 38
[BX+DI] 001 01 09 11 19 21 29 31 39
[BP+SI] 010 02 0A 12 1A 22 2A 32 3A
[BP+DI] 011 03 0B 13 1B 23 2B 33 3B
[SI] 100 04 0C 14 1C 24 2C 34 3C
[DI] 101 05 0D 15 1D 25 2D 35 3D
disp16 110 06 0E 16 1E 26 2E 36 3E
[BX] 111 07 0F 17 1F 27 2F 37 3F
[BX+SI]+disp8 01 000 40 48 50 58 60 68 70 78
[BX+DI]+disp8 001 41 49 51 59 61 69 71 79
[BP+SI]+disp8 010 42 4A 52 5A 62 6A 72 7A
[BP+DI]+disp8 011 43 4B 53 5B 63 6B 73 7B
[SI]+disp8 100 44 4C 54 5C 64 6C 74 7C
[DI]+disp8 101 45 4D 55 5D 65 6D 75 7D
[BP]+disp8 110 46 4E 56 5E 66 6E 76 7E
[BX]+disp8 111 47 4F 57 5F 67 6F 77 7F
[BX+SI]+disp16 10 000 80 88 90 98 A0 A8 B0 B8
[BX+DI]+disp16 001 81 89 91 99 A1 A9 B1 B9
[BP+SI]+disp16 010 82 8A 92 9A A2 AA B2 BA
[BP+DI]+disp16 011 83 8B 93 9B A3 AB B3 BB
[SI]+disp16 100 84 8C 94 9C A4 AC B4 BC
[DI]+disp16 101 85 8D 95 9D A5 AD B5 BD
[BP]+disp16 110 86 8E 96 9E A6 AE B6 BE
[BX]+disp16 111 87 8F 97 9F A7 AF B7 BF
AL/AX/EAX/ST0/MM0/XMM0 11 000 C0 C8 D0 D8 E0 E8 F0 F8
CL/CX/ECX/ST1/MM1/XMM1 001 C1 C9 D1 D9 E1 E9 F1 F9
DL/DX/EDX/ST2/MM2/XMM2 010 C2 CA D2 DA E2 EA F2 FA
BL/BX/EBX/ST3/MM3/XMM3 011 C3 CB D3 DB E3 EB F3 FB
AH/SP/ESP/ST4/MM4/XMM4 100 C4 CC D4 DC E4 EC F4 FC
CH/BP/EBP/ST5/MM5/XMM5 101 C5 CD D5 DD E5 ED F5 FD
DH/SI/ESI/ST6/MM6/XMM6 110 C6 CE D6 DE E6 EE F6 FE
BH/DI/EDI/ST7/MM7/XMM7 111 C7 CF D7 DF E7 EF F7 FF
ModR/M Note 1: Debug Registers DR4 and DR5
References to debug registers DR4 and DR5 cause an undefined opcode (#UD) exception to be generated when CR4.DE[bit 3] (Debugging Extensions) set; when clear, processor aliases references to registers DR4 and DR5 to DR6 and DR7 for compatibility with software written to run on earlier IA-32 processors.

Your Notes: